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A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving $-$46 dB TX/RX EVM Floor at 7.1 GHz for a 4 K-QAM 320 MHz Signal IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-22 Jongsoo Lee, Jaehyuk Jang, Wooseok Lee, Bosung Suh, Heeyong Yoo, Beomyu Park, Jeongkyun Woo, Inhyo Ryu, Honggul Han, Jaeyoung Kim, Hojung Kang, John H. Kang, Minseob Lee, Danbi Lee, Hyeonuk Son, Suhyeon Lee, Soyeon Kim, Dong-Chan Kim, Dae-Young Yoon, Hongjong Park, Sangsung Lee, Jeongyeol Bae, Huijung Kim, Joonhee Lee, Sangmin Yoo
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A 256 $\times$ 192-Pixel Direct Time-of-Flight LiDAR Receiver With a Current-Integrating-Based AFE Supporting 240-m-Range Imaging IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-21 Chaorui Zou, Yaozhong Ou, Yan Zhu, Rui P. Martins, Chi-Hang Chan, Minglei Zhang
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Compute SNDR-Boosted 22-nm MRAM-Based In-Memory Computing Macro Using Statistical Error Compensation IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-20 Saion K. Roy, Han-Mo Ou, Mostafa G. Ahmed, Peter Deaville, Bonan Zhang, Naveen Verma, Pavan K. Hanumolu, Naresh R. Shanbhag
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3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-19 Yoshiaki Osada, Takaaki Nakazato, Yumito Aoyagi, Koji Nii, Jhon-Jhy Liaw, Shien-Yang Wu, Quincy Li, Hidehiro Fujiwara, Hung-Jen Liao, Tsung-Yung Jonathan Chang
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A 1.8% FAR, 2 ms Decision Latency, 1.73 nJ/Decision Keywords-Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-IF-Domain Computing and Scalable 5T-SRAM IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-16 Fei Tan, Wei-Han Yu, Jinhai Lin, Ka-Fai Un, Rui P. Martins, Pui-In Mak
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A 70–86-GHz Deep-Noise-Canceling LNA With Dual-Stage Noise Cancellation Using Asymmetric Compensation Transformer and 4-to-1 Hybrid-Phase Combiner IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-14 Changxuan Han, Jie Zhou, Xun Luo
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PICO-RAM: A PVT-Insensitive Analog Compute-In-Memory SRAM Macro With In Situ Multi-Bit Charge Computing and 6T Thin-Cell-Compatible Layout IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-13 Zhiyu Chen, Ziyuan Wen, Weier Wan, Akhil Reddy Pakala, Yiwei Zou, Wei-Chen Wei, Zengyi Li, Yubei Chen, Kaiyuan Yang
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A 121.7-dB DR and $-$109.0-dB THD$+$N Filterless Digital-Input Class-D Amplifier With an HV IDAC Using Tri-Level Unit Cells IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-13 Huajun Zhang, Mingshuang Zhang, Mengying Chen, Arthur Admiraal, Miao Zhang, Marco Berkhout, Qinwen Fan
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A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-12 Luca Ricci, Gabriele Bè, Michele Rocco, Lorenzo Scaletti, Gabriele Zanoletti, Luca Bertulessi, Andrea L. Lacaita, Salvatore Levantino, Carlo Samori, Andrea Bonfanti
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A 4 $\times$ 112 Gb/s PAM-4 Silicon-Photonic Transmitter and Receiver Chipsets for Linear-Drive Co-Packaged Optics IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-08-12 Han Liu, Zhihan Zhang, Ye Liu, Daigao Chen, Donglai Lu, Jian He, Guike Li, Min Liu, Ziyue Dang, Xi Xiao, Nan Qi
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A Dynamic Execution Neural Network Processor for Fine-Grained Mixed-Precision Model Training Based on Online Quantization Sensitivity Analysis IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-28 Ruoyang Liu, Chenhan Wei, Yixiong Yang, Wenxun Wang, Binbin Yuan, Huazhong Yang, Yongpan Liu
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A Radiation-Hardened 15–22-GHz Frequency Synthesizer in 22-nm FinFET IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-28 David Dolt, Samuel Palermo
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Introduction to the Special Issue on the 2023 Symposium on VLSI Circuits IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-27 Mototsugu Hamada, Ron Kapusta
This Special Issue of IEEE Journal of Solid-State Circuits highlights some of the outstanding circuit papers presented at the Symposium on VLSI Technology and Circuits. The Symposium was held in person, June 11–16, 2023, in Kyoto, Japan.
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TechRxiv: Share Your Preprint Research with the World! IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-27
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Corrections to “A Synchronized Switch Harvesting Rectifier With Reusable Storage Capacitors for Piezoelectric Energy Harvesting” IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-27 Xinling Yue, Sijun Du
In the above article [1] , page 2605, the changes in Table II are as follows.
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A 2.8 $\mu$s Response Time 95.1% Efficiency Hybrid Boost Converter With RHP Zero Elimination for Fast-Transient Applications IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-27 Junyi Ruan, Junmin Jiang, Chenzhou Ding, Yunxiao Li, Yanhui Wu, Ka Nang Leung, Xun Liu
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A Single-Stage Dual-Output Regulating Voltage Doubler for Wireless Power Transfer IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-26 Tianqi Lu, Kofi A. A. Makinwa, Sijun Du
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A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-26 Jaekwang Yun, Sangyoon Lee, Jaewook Kim, Joo-Hyung Chae, Suhwan Kim, Yong-Un Jeong
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INTIACC: A Programmable Floating-Point Accelerator for Partial Differential Equations IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-26 Paul Xuanyuanliang Huang, Yannis Tsividis, Mingoo Seok
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A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-25 An Guo, Xi Chen, Fangyuan Dong, Xingyu Pu, Dongqi Li, Jingmin Zhang, Xueshan Dong, Hui Gao, Yiran Zhang, Bo Wang, Jun Yang, Xin Si
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A 50-Gb/s Multicarrier Transmitter Using DAC-Based Polar Drivers in 22-nm FinFET IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-25 Il-Min Yi, Srujan Kumar Kaile, Yuanming Zhu, Julian Camilo Gomez Diaz, Sebastian Hoyos, Samuel Palermo
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An IEEE 802.15.4/4z Coherent Quadrature Hybrid Correlation UWB Receiver in 65-nm CMOS IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-21 Yunzhao Nie, Woogeun Rhee, Zhihua Wang
This article presents a coherent ultra-wideband (UWB) receiver architecture based on a quadrature hybrid correlation (QHC) method that significantly reduces the digital-correlation-relevant power in the conventional standard-compliant UWB receiver. The proposed QHC receiver front end employs analog correlation, two-step synchronization with a digital-assisted path, and time-interleaved (TI) sampling
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A 26-Gb/s Framed-Pulsewidth Modulation Transceiver for Extended Reach Optical Links IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-21 Woohyun Kwon, Hyosup Won, Taeho Kim, Sejun Jeon, Soon-Won Kwon, Ha-Il Song, Hanho Choi, Bong-Jin Kim, Huxian Jin, Jun-Gi Jo, Woosang Han, Tai-Young Kim, Gain Kim, Jake Eu, Jinho Park, Hyeon-Min Bae
This article proposes a high-speed framed-pulsewidth modulation (FPWM) transceiver that applies a time-domain modulation scheme for increased spectrum efficiency. The achieved coding gain is 75%, indicating that the minimum pulsewidth is increased by 1.75 times compared to an NRZ scheme with an identical data rate. Such bandwidth reduction renders dispersion tolerance both in copper and optical channels
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An Energy-Efficient Neural Network Accelerator With Improved Resilience Against Fault Attacks IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-20 Saurav Maji, Kyungmi Lee, Cheng Gongye, Yunsi Fei, Anantha P. Chandrakasan
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A Compute-in-Memory Annealing Processor With Interaction Coefficient Reuse and Sparse Energy Computation for Solving Combinatorial Optimization Problems IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-19 Yifeng Zhou, Guocheng Su, Jinrong Zhou, Lei Liao, Zhuojun Chen
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DiTTO: A Distance Adaptive Over 100-mW Wireless Power Transfer System With 1.695-Mb/s Uplink Telemetry and a Shared Inductor Two-Output Regulating Rectification IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-19 Hongkyun Kim, Yechan Park, Changhoon Sung, Jaeouk Cho, Seongjun Park, Chul Kim
This article presents a wireless power transfer (WPT) system that incorporates a seamless uplink data telemetry and a simultaneous shared inductor dual-output (SIDO) regulating rectification (RR) under distance variation over a single WPT link. The proposed double charging keying (DCK) uplink data modulation method assisted by a dynamic zoom control breaks the trade-off between power delivery to the
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A 13.56-MHz Single-Input Dual-Output Wireless Power and Data Transfer System for Bio-Implants IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-19 Yang Liu, Yuan Yao, Wing-Hung Ki
A 13.56-MHz single-input dual-output (SIDO) wireless power and data transfer (WPDT) system designed for bio-implants is presented. The system incorporates a reconfigurable power amplifier (RPA) and an SIDO rectifier that generates regulated outputs of 1.2 and 2.5 V for different functional blocks of a bio-implant. A dynamic power distribution (DPD) scheme is employed to adjust the duty ratios of the
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A 300-$\mu$W 2.4-GHz PVT-Insensitive Subthreshold Reference-Based LNA IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-18 Martin Lee, Motaz Mohamed Elbadry, Kambiz Moez
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Analysis and Design of a 10.4-ENOB 0.92–5.38-$\mu$W Event-Driven Level-Crossing ADC With Adaptive Clocking for Time-Sparse Edge Applications IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-18 Jonah Van Assche, Georges Gielen
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A 6 to 12-GHz Fractional-$N$ Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-13 Aditya Narayanan, Abhishek Bhat, Nagendra Krishnapura
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A Battery-Free Neural-Recording Chip Achieving 5.5 cm Fully-Implanted Depth by Galvanically-Switching Passive Body Channel Communication IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-12 Yili Shen, Changgui Yang, Yunshan Zhang, Weixiao Wang, Yuxuan Luo, Chaonan Yu, Kedi Xu, Gang Pan, Bo Zhao
Wireless fully implanted devices are widely adopted for long-term neural-recording applications, where the cable-induced infection risk can be avoided. Battery-free communication based on wireless power transfer (WPT) can eliminate the battery to reduce the size of a wireless implant, realizing minimally invasive surgery. However, conventional battery-free implants suffer from a short communication
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SP-PIM: A Super-Pipelined Processing-In-Memory Accelerator With Local Error Prediction for Area/Energy-Efficient On-Device Learning IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-12 Jaehoon Heo, Jung-Hoon Kim, Wontak Han, Jaeuk Kim, Joo-Young Kim
Over the past few years, on-device learning (ODL) has become an integral aspect of the success of edge devices that embrace machine learning (ML) since it plays a crucial role in restoring ML model accuracy when the edge environment changes. However, implementing ODL on battery-limited edge devices poses significant challenges due to the generation of large-size intermediate data during ML training
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An Energy-Efficient Discrete-Time Delta–Sigma Modulator With Dynamic-Range Enhancement and Tri-Level CDAC IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-12 Cong Wei, Rongshan Wei, Lijie Huang, Gongxing Huang, Jinze Lai, Zhichao Tan
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A 0.68-THz Receiver With Third-Order Subharmonic Mixing in 65-nm CMOS IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-03-06 Kaizhe Guo, Chi Hou Chan
This article presents a 0.68-THz receiver with the third-order subharmonic mixing in a 65-nm CMOS technology. In this work, a third-order subharmonic mixer based on a double-balanced topology is proposed. The spurious mixing product of the mixer is utilized to increase the IF output of the mixer, thus improving the conversion gain and noise figure of the mixer. Besides, compensating capacitors are
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An Enhanced Class-F Dual-Core VCO With Common-Mode-Noise Self-Cancellation and Isolation Technique IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-02-29 Qixiu Wu, Wei Deng, Yaqian Sun, Haikun Jia, Hongzhuo Liu, Shiwei Zhang, Zhihua Wang, Baoyong Chi
In this article, an enhanced class-F voltage-controlled oscillator (VCO) with common-mode-noise self-cancellation (CM-NC) and common-mode-noise isolation (CM-NI) technique is proposed. With the proposed CM-NC technique, the common-mode-noise current of the drain coil and that of the nearby source coil are in the opposite direction. Therefore, the magnetic fields generated by the two coils cancel each
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RoboVisio: A Micro-Robot Vision Domain-Specific SoC for Autonomous Navigation Enabling Fully-on-Chip Intelligence via 2-MB eMRAM IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-02-27 Qirui Zhang, Zichen Fan, Hyochan An, Zhehong Wang, Ziyun Li, Guanru Wang, Pierre Abillama, Hun-Seok Kim, David Blaauw, Dennis Sylvester
This article presents RoboVisio, an efficient and highly flexible domain-specific system-on-chip (SoC) for vision tasks in fully autonomous micro-robot navigation. A novel hybrid processing element (PE) is proposed, in which classic vision tasks achieve high efficiency by using a 2-D-mapping architecture, while convolutional neural network (CNN) is executed in an efficient output-channel-parallel systolic
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Guest Editorial 2023 Custom Integrated Circuits Conference IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-02-26 Yan Lu, Shaolan Li
This Special Issue of the IEEE Journal of Solid-State Circuits (JSSC) features expanded versions of key articles presented at the 2023 Custom Integrated Circuits Conference (CICC), which was an in-person event held in San Antonio, TX, USA, from April 23 to 26, 2023. As the world’s premier conference devoted to integrated circuit (IC) development, CICC remains a vibrant forum for sharing the state-of-the-art
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A 64-Channel Inverter-Based Neural Signal Recording Amplifier With a Novel Differential-Like OTA Achieving an NEF of 0.84 IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-02-26 Qiuzhen Xu, Gen Li, Yanyan Liu, Feng Luo, Zhiming Xiao
This article presents an inverter-based multichannel low-power low-noise neural signal recording amplifier with a novel differential-like operational transconductance amplifier (OTA). The differential-like OTA consists of two asymmetric branches. The inverting branch used for multichannel inputs has more inverters in parallel than that of the noninverting branch used for reference. Two virtual rails
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TechRxiv: Share Your Preprint Research with the World! IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-02-26
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A Dual-Path Transformer-Based Multiband Power Amplifier for mm-Wave 5G Applications IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-02-21 Mohammad Ali Mokri, Soodeh Miraslani, Md Aminul Hoque, Deukhyoun Heo
This article presents a dual-band power amplifier for 28 and 39 GHz frequency bands based on a new dual-path transformer (DPT). This DPT can provide two optimum inductive values at two different frequency bands to optimally design the matching networks for each band without using any switch circuitries. It operates as the output and input matching networks in a parallel power combiner and divider,
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A Cryo-CMOS DAC-Based 40-Gb/s PAM4 Wireline Transmitter for Quantum Computing IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-02-21 Niels Fakkel, Mohsen Mortazavi, Ramon W. J. Overwater, Fabio Sebastiano, Masoud Babaie
Addressing the advancement toward large-scale quantum computers, this article presents the first four-level pulse amplitude modulation (PAM4) wireline transmitter (TX) operating at cryogenic temperatures (CTs). With quantum computers scaling up toward thousands of quantum bits (qubits), but having too limited fidelity for robust operation, continuous rounds of quantum error correction (QEC) are necessary
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A 10.8–14.5-GHz Eight-Phase 12.5%-Duty-Cycle Nonoverlapping LO Generator With Automatic Phase-and-Duty-Cycle Calibration IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-02-19 Khoi T. Phan, Yang Gao, Howard C. Luong
A 10.8–14.5-GHz eight-phase 12.5%-duty-cycle nonoverlapping LO generator is proposed for 60-GHz eight-path-filtering subsampling receivers. A four-stage ring oscillator (RO) is followed by reconfigurable injection-locked-oscillator NOR gates to generate eight-phase 12.5%-duty-cycle signals featuring automatic successive phase calibration and automatic frequency-domain duty-cycle calibration. The generator
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A Compact 19.7- to 43.8-GHz Power Amplifier With 20.3-dBm Psat and 35.5% PAE in 28-nm Bulk CMOS IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-02-19 Weisen Zeng, Li Gao, Ning-Zheng Sun, Hui-Yang Li, Jin-Xu Xu, Hongtao Xu, Quan Xue, Xiuyin Zhang
This article presents a broadband millimeter-wave (mm-wave) linear power amplifier (PA) to support 5G and beyond wireless communication. An asynchronously tuned coupled resonator (ATCR) circuit model is introduced to effectively design PA’s non-ideal transformer-based broadband output matching network (OMN). Two adaptive feedback linearizers (AFLs) and multi-gated transistor (MGTR) techniques are adapted
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A Fractional-N Sampling PLL With a Merged Constant-Slope DTC and Sampling PD IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-02-16 Gaofeng Jin, Fei Feng, Wen Chen, Yiyang Shu, Xun Luo, Xiang Gao
This article presents a 3.3–4.5-GHz fractional- $N$ analog sampling phase-locked loop (SPLL). A merged constant-slope digital-to-time converter and sampling phase detector (CSDTC-SPD) allows phase error detection as well as quantization noise (QN) cancellation in a single ramp generation, which reduces the source of noise and nonlinearity. A modified multimodulus divider (MMDIV) with two phase retimers
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A 116-Gb/s PAM4 0.9-pJ/b Transmitter With Eight-Tap FFE in 5-nm FinFET IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-02-16 Yevgeny Perelman, Zeev Toroker, Daljeet Kumar, Eran Maday, Noam Familia, Tzachi Carbone, Gal Kidron, Idan Mizrahi, Yoni Landau, Rushdy Saba, Yaakov Goldberg, Alon Meisler
This article presents a 116-Gb/s PAM4 voltage-mode (VM) transmitter (TX). The TX includes a 4:1-multiplexed 7-bit digital-to-analog converter (DAC) driver with an eight-tap feedforward equalizer (FFE). A high energy efficiency of 0.9 pJ/bit was achieved by novel data and clock path architectures that operate at up to 14.5 GHz. In the data path, the serializer is based mainly on MUXes that are biased
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Scaling-CIM: eDRAM In-Memory-Computing Accelerator With Dynamic-Scaling ADC and Adaptive Analog Operation IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-02-16 Sangjin Kim, Soyeon Um, Wooyoung Jo, Jingu Lee, Sangwoo Ha, Zhiyong Li, Hoi-Jun Yoo
This article presents Scaling-computing-in-memory (CIM), an energy-efficient embedded dynamic random access memory (eDRAM)-based in-memory-computing (IMC) accelerator with a dynamic-scaling readout for signal-to-quantization-noise ratio (SQNR) boosting and analog-to-digital converter (ADC) overhead reduction. It greatly saves the ADC cost by reducing the required number of ADC-bit and ADC operations
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A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-02-16 Shengzhe Yan, Jinshan Yue, Chaojie He, Zi Wang, Zhaori Cong, Yifan He, Mufeng Zhou, Wenyu Sun, Xueqing Li, Chunmeng Dou, Feng Zhang, Huazhong Yang, Yongpan Liu, Ming Liu
Computing-in-memory (CIM) chips have demonstrated promising high energy efficiency on multiply–accumulate (MAC) operations for artificial intelligence (AI) applications. Though integral (INT) CIM chips are emerging, the floating-point (FP) CIM chip has not been well explored. The high-accuracy demand of larger models and complex tasks requires FP computation. Besides, most of the neural network (NN)
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A High-Efficiency 40.68-MHz Single-Stage Dual-Output Regulating Rectifier With ZVS and Synchronous PFM Control for Wireless Powering IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-02-16 Ziyang Luo, Jin Liu, Hoi Lee
This article presents a 40.68-MHz single-stage dual-output regulating (SSDOR) rectifier, which has a new rectifier topology with only three active diodes for producing two outputs. Zero-voltage switching (ZVS) turn-on control for each active diode is developed to minimize converter power loss when rectifying 40.68-MHz input ac voltage. Synchronous PFM control is also proposed to regulate both outputs
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A Fully Dynamic Event-Driven Capacitive Sensor Interface Circuits Based on Self-Reconfigurable SAR Capacitance-to-Digital Conversion for High-Density Robotic Tactile Sensing IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-02-15 Yekan Chen, Tianyi Cai, Yonghong Kuang, Jiaqi Dong, Zipeng Cheng, Bo Zhao, Yuxuan Luo
Covering robots entirely with electronic skins (e-skins) has been a long-term aspiration. However, the number and density of the tactile sensors are limited by factors such as routing complexity, signal latency, and power consumption. Inspired by neural signal processing, we present a multichannel capacitive interface circuits that read out the sparse tactile signals in an event-driven (ED) manner
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An SNR-Enhanced 8-Ary (SNRE-8) Modulation Technique for Wireline Transceivers Using Pulse Width, Position, and Amplitude Modulation IEEE J. Solid-State Circuits (IF 4.6) Pub Date : 2024-02-14 Mohamed Megahed, Yusang Chun, Zhiping Wang, Tejasvi Anand
This article presents a novel eight-ary modulation technique with improved signal-to-noise ratio (SNR) compared to conventional pulse amplitude modulation 8 (PAM-8). The proposed SNR-enhanced 8-ary (SNRE-8) scheme modulates pulse width, position, and amplitude to improve the SNR. The proposed SNRE-8 modulation leverages the wireline channel loss to perform the modulation. Digital decoding of mutually