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A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm$^{2}$ Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture
IEEE Journal of Solid-State Circuits ( IF 4.6 ) Pub Date : 2024-12-12 , DOI: 10.1109/jssc.2024.3509958 Masaru Haraguchi, Yorinobu Fujino, Yoshisato Yokoyama, Ming-Hung Chang, Yu-Hao Hsu, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang
中文翻译：
一个 3 nm-FinFET 4.3 GHz 21.1 mb/mm$^{2}$ 双泵 1 读和 1 写伪 2 端口 SRAM，采用折叠位线多区架构
更新日期：2024-12-12
IEEE Journal of Solid-State Circuits ( IF 4.6 ) Pub Date : 2024-12-12 , DOI: 10.1109/jssc.2024.3509958 Masaru Haraguchi, Yorinobu Fujino, Yoshisato Yokoyama, Ming-Hung Chang, Yu-Hao Hsu, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang
中文翻译：
一个 3 nm-FinFET 4.3 GHz 21.1 mb/mm$^{2}$ 双泵 1 读和 1 写伪 2 端口 SRAM，采用折叠位线多区架构
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