This paper proposes an inductor-less D-latch. In the proposed D-latch, negative feedback is used that makes input impedance appears to be inductive for the high-frequency input signal. The bandwidth is increased by around 23% due to this effect. Two applications are shown in this paper to verify the proposed latch operation: a pseudo-random binary sequence (PRBS) generator and a serializer. The speed of the PRBS generator and serializer has improved by 15.8% and 23% using the proposed latch, respectively. The post-layout simulation results in 90 nm CMOS technology with a power supply of 1 V prove the concept. To study functional correctness and scalability of the proposed architecture to lower technology nodes, 22 nm PTM model is used and verified the correct operation of the proposed architecture.

本文提出了一种无电感的 D 型锁存器。在所提议的 D 锁存器中，使用了负反馈，使得输入阻抗对于高频输入信号而言似乎是电感性的。由于这种效果，带宽增加了大约 23%。本文展示了两个应用程序来验证所提出的锁存操作：伪随机二进制序列 (PRBS) 生成器和串行器。使用建议的锁存器，PRBS 发生器和串行器的速度分别提高了 15.8% 和 23%。90 nm CMOS 技术和 1 V 电源的布局后仿真结果证明了这一概念。为了研究所提出架构对较低技术节点的功能正确性和可扩展性，使用 22 nm PTM 模型并验证所提出架构的正确操作。