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1.T. Al-Ameri, V. P. Georgiev, T. Sadi, Y. Wang, F. Adamu-Lema,X. Wang, S. M. Amoroso, E. Towie, A. R. Brown and A. Asenov, "Impact of Quantum Confinement on Transport and the Electrostatic Driven Performance of Silicon Nanowire Transistors at the Scaling Limit,"Solid-State Electronics, Vol. 129, pp. 73–80, Mar. 2017. 2.Y. Wang, B. Cheng,X. Wang, E. Towie, C. Riddet, A. R. Brown, S. M. Amoroso, L. Wang, D. Reid, X. Liu, J. Kang and A. Asenov, "Variability-aware TCAD Based Design-Technology Co-Optimization Platform for 7nm Node Nanowire and Beyond," inProc. Symposium on VLSI Technology Digest of Technical Papers (VLSI-Tech), Honolulu HI USA, June 13-16, 2016, pp. 174–175. 3.A. Asenov, Y. Wang, B. Cheng,X. Wang, P. Asenov, T. Al-Ameri and V. Georgiev, “Nanowire transistor solutions for 5nm and beyond,” in Proc 17thInternational Symposium on Quality Electronic Design (ISQED), Santa Clara, USA, March 15-16, 2016, pp.269-274. (邀请论文，执笔) 4.Z. Zhang, Z. Zhang, R. Wang*, X. Jiang, S. Guo, Y. Wang,X. Wang*, B. Cheng, A. Aseov and R. Huang, "New Approach for Understanding “Random Device Physics” from Channel Percolation Perspectives: Statistical Simulations, Key Factors and Experimental Results," inProc. IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Dec. 5-7, 2016, pp. 172–175. 5.X. Jiang, S. Guo, R. Wang*,X. Wang*, B. Cheng, A. Asenov, and R. Huang, “A device-level characterization approach to quantify the impacts of different random variation sources in FinFET technology,”IEEE Electron Device Letters,Vol.37 no.8, pp.932-935, August 2016. doi:10.1109/LED.2016.2581878 6.X. Jiang, S. Guo, R. Wang, Y. Wang,X. Wang, B. Cheng, A. Asenov and R. Huang, "New Insights into the Near-Threshold Design in Nanoscale FinFET Technology for Sub-0.2V Applications," inProc. International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Dec. 5-9, 2016, pp. 695–698. 7.X. Wang, B. Cheng, D. Reid, A. Pender, P. Asenov, C. Millar, and A. Asenov, “FinFET centric variability-aware compact model extraction and generation technology supporting DTCO,”IEEE Transactions on Electron Devices,vol.62 no.10, pp.3139-3146, Oct. 2015. 8.Y. Wang, T. Al-Ameri,X. Wang*, V. Georgiev, E. Towie, S. M. Amoroso, A.R. Brown, B. Cheng, D. Reid, C. Riddet, L. Shifren, S. Sinha, G. Yeric, R. Aitken, X. Liu, J. Kang, and A. Asenov*, “Simulation study of the impact of quantum confinement on the electrostatically driven performance of nanowire transistors,”IEEE Transactions on Electron Devices, vol.62 no.10, pp.3299-3236, Oct. 2015. 9.X. Jiang,X. Wang*, R. Wang*, B. Cheng, A. Asenov and R. Huang*, "Predictive Compact Modeling of Random Variations in FinFET Technology for 16/14nm Node and Beyond," inProc. IEEE International Electron Devices Meeting (IEDM), Washington DC, Dec. 7-9, 2015, p. 28.3.1–28.3.4. 10.X. Jiang, J. Wang,X. Wang*, R. Wang*, B. Cheng, A. Asenov, L. Wei*, and R. Huang, “New Assessment Methodology Based on Energy–Delay–Yield Cooptimization for Nanoscale CMOS Technology,”IEEE Transactions on Electron Devices, Vol. 62 No. 6, pp.1746-1753, June 2015. 11.A. Asenov, B. Cheng,X. Wang, A. R. Brown, C. Millar, C. Alexander, S. M. Amoroso, J. B. Kuang and S. Nassif, "Variability Aware Simulation Based Design-Technology Co-optimization (DTCO) Flow in 14 nm FinFET/SRAM Cooptimization,"IEEE Transactions on Electron Devices, Vol. 62, No. 6, pp. 1682–1690, June 2015. (邀请论文，封面论文) 12.S. M. Amoroso, V. P. Georgiev, L. Gerrer, E. Towie,X. Wang, C. Riddet, A. R. Brown and A. Asenov, "Inverse Scaling Trends for Charge-Trapping-Induced Degradation of FinFETs Performance,"IEEE Transactions on Electron Devices, Vol. 61, No. 12, pp. 4014–4018, Oct. 2014. 13.F. Adamu-Lema#,X. Wang#, S. M. Amoroso, C. Riddet, B. Cheng, L. Shifren, R. Aitken, S. Sinha, G. Yeric, A. Asenov, “Performance and variability of doped multi-threshold FinFETs for 10nm CMOS,”IEEE Transactions on Electron Devices, vol.61 no.10, pp.3372-3378, Oct. 2014. 14.X. Wang, A.R. Brown, B. Cheng, S. Roy, and A. Asenov, “Drain Bias Effects on Statistical Variability and Reliability and Related Subthreshold Variability in 20-nm Bulk Planar MOSFETs,”Solid-State Electronics. Vol.98, pp.99-105, August 2014. 15.A. Asenov, F. Adamu-Lema,X. Wangand S. M. Amoroso, "Problems with the continuous doping TCAD simulations of decananometer CMOS transistors,"IEEE Transactions on Electron Devices, Vol. 61, No. 8, pp. 2745–2751, Aug. 2014. 16.A. Asenov, B. Cheng,X. Wang, A. R. Brown, D. Reid, C. Millar and C. L. Alexander, "Simulation Based Transistor-SRAM Co-Design in the Presence of Statistical Variability and Reliability," inProc. IEEE International Electron Devices Meeting (IEDM), Washington DC, Dec. 9-11, 2013, pp. 818–821. (邀请论文) 17.X. Wang, B. Cheng, A.R. Brown, C. Millar, J.B. Kuang, S. Nassif, A. Asenov, “Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm node SOI FinFET Technology,”IEEE Design & Test,vol.30 no.6, pp.18-28, December 2013. (邀请论文) 18.X. Wang, B. Cheng, A. R. Brown, C. Millar, J. B. Kuang, S. Nassif, and A. Asenov, “Interplay Between Process-Induced and Statistical Variability in 14-nm CMOS technology Double-Gate SOI FinFETs,”IEEE Transactions on Electron Devices, Vol.60 No.8, pp.2485-2492, August 2013. 19.X. Wang, F. Adamu-Lema, B. Cheng, and A. Asenov, “Geometry, Temperature and Body Bias Dependence of Statistical Variability of 22-nm Bulk CMOS Technology: A Comprehensive Simulation Analysis,”IEEE Transactions on Electron Devices, Vol.60 No.5, pp.1547-1554, May 2013. 20.X. Wang, G. Roy, O. Saxod, A. Bajolet, A. Juge, and A. Asenov, “Simulation Study of Dominant Statistical Variability Sources in 32-nm High-k/Metal Gate CMOS,”IEEE Electron Device Letters, Vol.33, No.5, pp.643-645, May 2012.
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