罗小蓉 - 电子科技大学 - 电子科学与工程学院

个人简介

教育背景 2007年，电子科技大学，博士学位 2001年，四川大学，硕士学位工作履历 2001年7月-至今，电子科技大学工作； 2009-2010年到英国剑桥大学进行博士后研究； 2011年聘为博士生导师，2012年破格晋升教授；现任微电子与固体电子学系主任。

研究领域

1：可集成功率半导体器件研究内容提出并研究新型SOI横向功率MOSFET新结构及机理，设计其应用集成电路，将新型MOSFET用作其功率晶体管，并实现高低压集成。 >2：功率半导体器件研究内容研究高性能的MOSFET新结构及其工作机理，并研制新型MOSFET样品或者产品，实现提升耐压、降低导通电阻及高可靠性 3：高低压集成技术研究内容设计高压集成电路，含体硅基、SOI基的高压集成电路，并设计新型可集成高压器件，符合要求的SOI材料的设计，考虑高低压工艺兼容技术。

近期论文

查看导师新发文章（温馨提示：请注意重名现象，建议点开原文通过作者单位确认）

[1] Kun Zhou, Linhua Huang, Xiaorong Luo*, Zhaoji Li; Bo Zhang.Characterization and Performance Evaluation of the Superjunction RB-IGBT in Matrix Converter,IEEE Transactions on Power Electronics, DOI: 10.1109/TPEL.2017.2709323,2018. [2] Jie Wei;Xiaorong Luo*; Linhua Huang; Bo Zhang,Simulation Study of a Novel Snapback-Free and Low Turn-Off Loss Reverse-Conducting IGBT With Controllable Trench Gate IEEE Electron Device Lett.,DOI: 10.1109/LED.2017.2780081,2018. [3] Gaoqiang Deng, Xiao Rong Luo, Jie Wei et al.A Snapback-Free Reverse Conducting Insulated-Gate Bipolar Transistor With Discontinuous Field-Stop Layer,IEEE Transactions on Electron Devices,DOI: 10.1109/TED.2018.2817204, 2018. [4] linhua Huang;Xiaorong Luo*; Jie Wei; Kun Zhou et al;A Snapback-Free Fast-Switching SOI LIGBT With Polysilicon Regulative Resistance and Trench Cathode,IEEE Transactions on Electron Devices,DOI: 10.1109/TED.2017.2726080,2017. [5] Weiwei Ge, Xiaorong Luo*, Junfeng Wu,et al.Ultra-low On-Resistance LDMOS with Multi-plane Electron Accumulation Layers,IEEE Electron Device Lett., DOI: 10.1109/LED.2017.2701354,2017. [6] Xiaorong Luo, Qiao Tan，Jie Wei，Kun Zhou，Gaoqiang Deng，Zhaoji,Ultralow On-Resistance High Voltage p-channel LDMOS with an Accumulation-Effect Extended Gate, IEEE Transactions on Electron Devices, 63(6), p.2614, 2016. [7] Xiaorong Luo*, Da Ma, Jie Wei , et al. A split gate power FINFET with improved on-resistance and switching performance, IEEE Electron Device Lett.,37(9),p.1185, 2016. [8] Xiaorong Luo*, Mengshan Lv, et al. Ultralow On-Resistance SOI LDMOS with Three Separated Gates and High-K Dielectric, IEEE Transactions on Electron Devices, 66(9), p.3804, 2016. [9] Kun Zhou, Xiaorong Luo*, Linhua Huang, et al.,An Ultralow Loss Superjunction Reverse Blocking Insulated-Gate Bipolar Transistor with Shorted-Collector Trench,DOI: 10.1109/LED.2016.2613638, 2016. [10] Jie Wei , Xiaorong Luo*, Yanhui Zhang，Pengcheng Li，Kun Zhou，Bo Zhang，Zhaoji Li, High Voltage Thin SOI LDMOS with Ultralow On-resistance and EvenTemperature Characteristic，IEEE Transactions on Electron Devices, 63(4),p.1637, 2016. [11] Kun Zhou, Xiaorong Luo*, Qing Xu, et al. Analytical Model and New Structure of the Variable-k Dielectric Trench LDMOS with Improved, IEEE Transactions on Electron Devices, 62(10), p.3334, 2015. [12] Xiaorong Luo, Y H Jiang, K Zhou, Bo Zhang et al. Ultra-low Specific On-Resistance Superjunction Vertical DMOS with High-K Dielectric Pillar, IEEE Electron Device Lett., 33(7) ,1042-1044, 2012. [13] Xiaorong Luo, J Fan, Bo Zhang Florin Udrea, Ultra-low Specific On-Resistance High Voltage SOI Lateral MOSFET, IEEE Electron Device Lett., 32(2), 185-187, 2011. [14] Xiaorong Luo, Yuangang Wang, Guoliang Yao, et al, High Voltage Partial SOI LDMOS with a Variable Low-k Dielectric Buried Layer and a Buried P-layer, IEEE Electron Device Lett., 31(6), 594-596, 2010. [15] Xiaorong Luo, Tianfei Lei, Bo Zhang, et al. A high-voltage LDMOS compatible with high voltage integrated circuits on p-type SOI layer, IEEE Electron Device Lett.,30(10),1093-1095, 2009. [16] Xiaorong Luo, Zhaoji Li, Bo Zhang, et al. Realization of High Voltage ( >700V) in New SOI Devices with a Compound Buried-Layer, IEEE Electron Device Lett.,29(12),pp.1395-1397, 2008. [17] Xiaorong Luo, Bo Zhang, Zhaoji Li, et al. A Novel 700-V SOI LDMOS with Double-Sided Trench, IEEE Electron Device Lett., 28(5): 422-424, 2007. [18] Xiaorong LuoJie Wei，Xianlong Shi，Kun Zhou，Ruichao Tian，Zhaoji Li，Bo Zhang ，Novel Reduced ON-Resistance LDMOS With an Enhanced Breakdown Voltage, IEEE Trans.on Electron Devices, 2014,61(12)：4304-4308. [19] Xiaorong Luo, J Y Cai, Y Fan,et al. Novel Low-Resistance Current path UMOS with High-K Dielectric Pillars,IEEE Trans. Electron Devices, 60(9), 2840-2846, 2013.