蒋剑飞 - 上海交通大学 - 微纳电子学系

个人简介

蒋剑飞，博士，助理研究员，硕士生导师，本科毕业于浙江大学，获工学学士学位，研究生毕业于上海交通大学，获电路与系统工学硕士学位，电子科学与技术工学博士学位。获国家留学基金委《青年骨干教师出国研修项目》资助，2013.7-2014.7 年期间美国北卡罗莱纳州立大学电子工程系访问学者。获国家外专局资助，2016.10～2016.11期间比利时鲁汶大学和欧洲微电子中心访问学者。有十多年数字集成电路设计工作经验，主要从事高速集成电路、三维低功耗集成电路、SoC体系结构与神经网络加速电路、高精度测量电路等方向的设计与研究。曾作为项目主要人员完成多个国家重大项目，包括国家重大专项，863项目，型谱项目和新品项目等，成功设计并流片包括数字信号处理器等多个SoC芯片。在集成电路领域在国内外期刊上发表SCI论文6篇，EI论文19篇，其他论文16篇，国家发明专利多项。

研究领域

1、高速集成电路/高速互连2、三维低功耗集成电路3、SoC体系结构与神经网络加速电路4、高精度测量电路

近期论文

查看导师新发文章（温馨提示：请注意重名现象，建议点开原文通过作者单位确认）

Qin Wang, Zhenyang Chen, Jianfei Jiang, Zheng Guo, Zhigang Mao，”Dynamic Data Split: A Crosstalk Suppression Scheme in TSV-Based 3D IC,” Integration, the VLSI Journal 59 (2017) 23–30. Jianfei Jiang, Zhigang Mao, Weiguang Sheng, Qin Wang and Weifeng He, “Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects,” Journal of Circuits, Systems, and Computers, Vol. 25, No. 10, p1-31, 2016. Jianfei Jiang, Weifeng He, Qin Wang, Zhigang Mao, “Design Optimization for Capacitive-resistively Driven On-chip Global Interconnect,” IEICE Electronics Express, Vol.12, No.8, p1-12, 2015. Zhiting Yan, Guanghui He, Yifan Ren, Weifeng He, Jianfei Jiang, Zhigang Mao, “Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 62, No.11, p2706-2717, 2015. Weiguang Sheng, Jianfei Jiang, Zhigang Mao, Parallel SER analysis for combinational and sequential standard cell circuits, Microelectronics Journal, Vol. 50, No. 4, pp. 8-19, 2016. N Jing, Jiachen Zhou, Jianfei Jiang, Xin Chen, Weifeng He, Zhigang Mao, “Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 764-769, 2015 Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao, “Contactless Testing Methodology for Pre-bond Interposer,” IEEE 58th International Midwest Symposium on Circuits and Systems (MWSWCAS), 2015. JianFei Jiang, WeiGuang Sheng, Zhigang Mao, Weifeng He, A Pre-emphasis Circuit Design for High Speed On-Chip Global Interconnect, IEEE International Symposium on Circuits and Systems (ISCAS),pp. 2941-2944, 2012. JianFei Jiang, Xu Wang, WeiGuang Sheng, Wei-feng He, Zhi-gang Mao, A clock-less transceiver for global interconnect, IEEE International Conference on VLSI and System-on-Chip (VLSI-SoC),pp.184-187,2011.