个人简介
2004年本科毕业于浙江大学，2010年获荷兰屯特大学Bram Nauta教授组最优等博士学位。2010年至2016年任职于美满电子科技Marvell加州硅谷总部，历任资深工程师，主任工程师，资深主任工程师，首席工程师以及研发经理，带领射频及模数混合信号研发团队负责Wifi无线通信以及物联网通信芯片的研发。2016年至2018年任美国默升科技Credo技术总监，领导团队用先进工艺如28nm,16nm 及7nm CMOS设计高速SerDes芯片。2018年入选浙大百人计划并于8月份加入浙江大学信电学院。长期致力于射频及模数混合信号集成电路设计的理论与研究，在锁相环技术，无线通信芯片和高速有线通信芯片的理论研究和产业化上均取得了重要的原创性成果，是目前流行的亚采样锁相环结构（Sub-Sampling PLL）发明人，现为IEEE 高级会员，领域最顶级会议ISSCC（被誉为“集成电路领域的奥林匹克”）学术委员会委员，同时也是领域重要会议RFIC和CICC的学术委员会委员，在国际知名期刊和会议上发表论文20多篇,其中ISSCC 6篇,持有8项第一发明人美国专利,根据谷歌学术搜索所发表论文被引用总数达600多次。
近期论文
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JOURNALS:
[J-1] R. Dutta, E. Klumperink, X. Gao, Z. Ru, R. van der zee and B. Nauta, “Flip-Flops for Accurate Multi-Phase Clocking: Transmission Gate versus Current Mode Logic”, IEEE Transaction on Circuits and Systems II (TCAS-II), pp.422-426,Jul. 2013.
[J-2]X. Gao, E. Klumperink, G. Socci, M. Bohsali and B. Nauta, “Spur Reduction Techniques for Phase-Locked Loops Exploiting a Sub-Sampling Phase Detector”, IEEEJournalofSolid-StateCircuits (JSSC), vol. 45, no.9, pp. 1809-1821, Sep. 2010.
[J-3]X. Gao, E. Klumperink, M. Bohsali and B. Nauta, “A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is not Multiplied by N2”, IEEEJournalofSolid-StateCircuits (JSSC), vol. 44, no.12, pp. 3253-3263, Dec. 2009. (Invited paper)
[J-4]X. Gao, E. Klumperink, P.J.F. Geraedts and B. Nauta, “Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops”, IEEE Transaction on Circuits and Systems II (TCAS-II), pp. 117-121, Feb. 2009.
[J-5]X. Gao, E. Klumperink and B. Nauta, “Advantages of Shift Registers Over DLLs for Flexible Low Jitter Multiphase Clock Generation”, IEEE Transaction on Circuits and Systems II (TCAS-II), pp. 244-248, Mar. 2008.
CONFERENCES:
[C-1]X. Gao, O. Burg, H. Wang, W. Wu, C.-T. Tu, K. Manetakis, F. Zhang, M. Yayla, S. Xiang, R. Tsang and L. Lin, “A 2.7-4.3GHz 0.16psrms Jitter -246.8dB FOM Digital Fractional-N Sampling PLL in 28nm CMOS”, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2016.
[C-2]R. Winoto, A. Olyaei, W. Lau, X. Gao, M. Hajirostam,et. al., “A 2x2 WLAN and Bluetooth Combo SoC in 28nm CMOS with On-Chip WLAN Digital Power Amplifier, Integrated 2G/BT SP3T Switch and BT Pulling Cancellation”, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2016.
[C-3]X. Gao, E. Klumperink and B. Nauta, “Sub-Sampling PLL Techniques', IEEE Custom Integrated Circuits Conference (CICC), 2015. (Invited paper)
[C-4]X. Gao, L. Tee, W. Wu, K.-S. Lee,A. A. Paramanandam, A. Jha, N. Liu, E. Chan and L. Lin, “A 28nm CMOS Digital Fractional-N PLL with -245.5dB FOM and a Frequency Tripler For 802.11abgn/ac Radio”, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2015.
[C-5]M. He, R. Winoto, X. Gao, W. Loeb, D. Signoff, W. Lau, Y. Lu, D. Cui, K.-S. Lee, S.-W. Tam. P. Godoy, Y. Chen, S. Joo, C. Hu, A. A. Paramanandam, X. Wang, C.-H. Lin and L. Lin, “A 40nm dual-band 3-stream 802.11a/b/g/n/ac MIMO WLAN SoC with 1.1Gb/s over-the-air throughput”, IEEE International Solid-State Circuits Conference (ISSCC), pp. 350-351, Feb. 2014.
[C-6]X. Gao, E. Klumperink, G. Socci, M. Bohsali and B. Nauta, “Spur-Reduction Techniques for PLLs Using Sub-Sampling Phase Detection”, IEEE International Solid-State Circuits Conference (ISSCC), pp. 474-475, Feb. 2010.
[C-7]X. Gao, E. Klumperink, M. Bohsali and B. Nauta, “A 2.2GHz 7.6-mW Sub-Sampling PLL with -126dBc/Hz In-band Phase Noise and 0.15psrms Jitter in 0.18-μm CMOS”, IEEE International Solid-State Circuits Conference (ISSCC), pp. 392-393, Feb. 2009.
[C-8]E. Klumperink, R. Dutta, Z. Ru, X. Gao and B. Nauta, 'Jitter-Power Minimization of Digital Frequency Synthesis Architectures',IEEE International Symposium on Circuits and Systems (ISCAS), pp. 165-169, May 2011. (Invited paper)
[C-9]X. Gao, E. Klumperink, G. Socci, M. Bohsali and B. Nauta, “A 2.2GHz Sub-Sampling PLL with 0.16psrms Jitter and -125dBc/Hz In-band Phase Noise at 700μW Loop-Components Power,” IEEE Symposium on VLSI Circuits, pp. 139-140, Jun. 2010.
[C-10]R. Dutta, T. K Bhattacharyya, X. Gao and E. A. M. Klumperink, “Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product”, 23rd International Conference on VLSI Design, pp.152-157, Jan. 2010.
[C-11]X. Gao, E. Klumperink, M. Bohsali and B. Nauta, “A PLL Exploiting Sub-Sampling of the VCO Output to Reduce In-band Phase Noise,” 20th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC), pp. 326-329, Nov. 2009.
[C-12]X. Gao, E. Klumperink, and B. Nauta, “Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2854-2857, May 2007.
[C-13]X. Gao, E. Klumperink and B. Nauta, “Comparing DLLs and Shift Registers for Low-Jitter Multi-phase Clock Generation,” 18th Annual Workshop on Circuits Systems and Signal Processing(ProRISC), pp.29-30,Nov. 2007.
BOOK AND BOOK CHAPTER:
[B-1] X. Gao, “Low Jitter Low Power Phase Locked Loops Using Sub-Sampling,” PhD thesis, University of Twente, ISBN-978-90-365-3022-4, 2010. URL:http://doc.utwente.nl/71770/
[B-2] E. Klumperink, X. Gao and B. Nauta,“Polyphase Multipath Circuits for Cognitive Radio and Flexible Multi-phase Clock Generation”,Chapter 7 in Circuits and Systems for Future Generations of Wireless Communications, Editors A. Tasic, et. al, ISBN 978-1-4020-9918-2, Springer, 2009.
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