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1. Z. Ying, C. Luo, X. Zhu, 'A Scalable Hardware Architecture for Multi-Layer Spiking Neural Networks', in IEEE 12th International Conference on ASIC (ASICON 2017), Guiyang, Oct. 2017.
2. L. Chen, Z. Ying, C. Luo and X. Zhu, 'A Four-Phase Dual-Rail Protocol based Asynchronous Arbiter for Neuromorphic Networks', in 2017 9th International Conference on Intelligent Human-Machine Systems and Cybernetics (IHMSC 2017), Hangzhou, Sep. 2017.
3. C. Luo, Z. Ying, X. Zhu and L. Chen, 'A Mixed-Signal Spiking Neuromorphic Architecture for Scalable Neural Network', in 2017 9th International Conference on Intelligent Human-Machine Systems and Cybernetics (IHMSC 2017), Hangzhou, Sep. 2017.
4. D. Ma, J. Shen, Z. Gu, M. Zhang, X. Zhu, X. Xu, Q. Xu, Y. Shen, G. Pan, 'Darwin: a neuromorphic hardware co-processor based on Spiking Neural Networks', Journal of Systems Architecture, 2017.
5. J. Shen, D. Ma, Z. Gu, M. Zhang, X. Zhu, X. Xu, Q. Xu, Y. Shen, G. Pan, 'Darwin: a neuromorphic hardware co-processor based on Spiking Neural Networks', SCIENCE CHINA Information Sciences 59(2): 1-5 (2016).
6. W. Wang, R. Huang, G. Sun and X. Zhu, 'A Digital Background Calibration Technique for Split DAC Based SAR ADC by Using Redundant Cycle', in 28th IEEE International System-on-Chip Conference (SOCC), Beijing, Sep. 2015.
7. W. Mao, L. Sun, J. Xu, J. Wu and X. Zhu, 'Analysis and Design of High Performance Wireless Power Delivery Using On-chip Octagonal Inductor in 65-nm CMOS', in 28th IEEE International System-on-Chip Conference (SOCC), Beijing, Sep. 2015.
8. R. Huang, L. Shao, W. Wang, G. Sun and X. Zhu, 'An Error Codes Detection Based Background Calibration for Split SAR ADC', in 2015 IEEE Electron Devices and Solid-state Circuits Conference (EDSSC), Singapore, Jun. 2015.
9. L. Sun, J. Xu, W. Mao, S. Zou, P. Lv and X. Zhu, '1GHz Wireless Power Delivery Using 0.2x0.2mm2 On-chip Inductor for 3-D Stacked Chips', in 2015 IEEE Electron Devices and Solid-state Circuits Conference (EDSSC), Singapore, Jun. 2015.
10. G. Sun, Y. Zhang, L. He and X. Zhu. “A Threshold Control Technique for CMOS Comparator Design,” in 2014 IEEE Electron Devices and Solid-state Circuits Conference (EDSSC), Chendu, Jun. 2014.
11. X. Xue, X. Zhu, Q. Shi, and L. He, “A 12-Bit 400-Ms/s Current-steering DAC with Deglitching Technique,” Journal of Circuits, Systems, and Computers, vol. 23, no.1, 1450004-1-13, Jan. 2014.
12. X. Zhu, Y. Chen, S. Tsukamoto, T. Kuroda, ' A 9-bit 100MS/s Tri-level Charge Redistribution SAR ADC with Asymmetric CDAC Array,' in 2012 International Symposium on VLSI Design, Automation and Test (2012 VLSI-DAT), Hsinchu, Taiwan, Apr. 2012.
13. X. Zhu, Y. Chen, S. Tsukamoto and T. Kuroda, 'A 9-bit 100MS/s SAR ADC with Digitally Assisted Background Calibration,' IEICE Transactions on Electronics, vol E95-C, no.6, pp.1026 -1034, Jun. 2012.
14. X. Zhu, Y. Chen, M. Kibune, Y. Tomita, T. Hamada, H. Tamura, S. Tsukamoto, and T. Kuroda, 'A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology,' IEICE Transactions on Fundamental of Electronics, Communications and Computer Sciences, vol. E93-A, no.12, pp. 2456-2462, Dec. 2010.
15. Y. Chen, X. Zhu, H. Tamura, M. Kibune, Y. Tomita, T. Hamada, M. Yoshioka, K. Ishikawa, T. Takayama, J. Ogawa, S. Tsukamoto and T. Kuroda, 'Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC,' in IEEE Custom Integrated Circuits Conference (CICC) Dig. Tech. Paper, pp. 279-282, San Jose, USA, sep. 2009.
16. X. Zhu, S. Tsukamoto, and T. Kuroda, 'A 1 GHz CMOS Comparator with Dynamic Offset Control Technique,' in 14th Asia and South Pacific Design Automation Conference (ASP-DAC), pp.103-104, Yokohama, Japan, Jan. 2009.
17. X. Zhu, Y. Chen, M. Kibune, Y. Tomita, T. Hamada, H. Tamura, S. Tsukamoto, and T. Kuroda, 'A dynamic offset control technique for comparator design in scaled CMOS technology,' in IEEE Custom Integrated Circuits Conference (CICC) Dig. Tech. Papers, pp.495-498, San Jose, USA, Sep. 2008.
18. Baoyong Chi, Xiaolei Zhu, Ziqiang Wang, Zhihua Wang, “Quadrature Oscillator with Negative-Resistance Compensated Transformer Couple”, Proceedings of Asian Solid-State Circuits Conference (A-SSCC 2005).
19. Chi Baoyong, Zhu Xiaolei, Wang Ziqiang, and Wang Zhihua, “Low Phase Noise Quadrature Oscillators Using New Injection Locked Technique”, Chinese Journal of Semiconductors,2005, 26(9): 49-54.
20. Chi Baoyong, Zhu Xiaolei, Huang Shuilong, Wang Zhihua, '1GHz Monolithic Fractional-N Frequency Synthesizer with a 3-b Third-Order Delta-Sigma Modulator', ACTA ELECTRONICA SINICA, Vol.33, No.8, 2005, pp.1492-1496. Language: Chinese.
21. Xiaolei Zhu, Jizhong Shen, Baoyong Chi and Zhihua Wang. Circuit implementation of Multi-Thresholded Neuron (MTN) using BiCMOS Technology. Proceedings of 2005 International Joint Conference of Neural Networks. July 31st, 2005, Montréal, Canada. pp.627-632.
22. Yao Mao-qun, Zhu Xiao-Lei, Shen Ji-Zhong. Circuits design of Multi-thresholded neuron and it's application in multi-valued logic. Chinese Journal of Computers, v28, n2, February, 2005, pp.281-288. Language: Chinese.
23. Baoyong Chi, Xiaolei Zhu, Shuilong Huang, Zhihua Wang. 1GHz Monolithic High Spectrum Purity Fractional-N Frequency Synthesizer with a 3-b Third-Order Delta-Sigma Modulator. Proceedings of the 7th International Conference on Solid-State and Integrated Circuits Technology, Volume II, pp.1504-1507. Beijing, China. Oct, 2004.
24. Zhu Xiao-Lei, Shen Ji-Zhong. Multi-thresholded neuron and it's application in multi-valued logic. Journal of Zhejiang University (Engineering Science Edition), v38, n5, May, 2004, pp.571-576. Language: Chinese.
25. Zhu Xiao-Lei, Shen Ji-Zhong. Design of low-voltage low-power ternary TTL circuits based on the technique of low threshold voltage. Journal of Zhejiang University (Engineering Science Edition), v 36, n6, November, 2002, pp.655-658. Language: Chinese.