刘波 - 东南大学 - 电子科学与工程学院

个人简介

刘波，东南大学电子科学与工程学院讲师，主要研究方向为低功耗智能计算架构与电路设计。先后负责国家自然科学基金1项、国家科技重大专项1项；并参与多项国家自然科学基金、863重点项目等国家级科研课题。作为技术骨干参与十一五、十二五863高能效计算架构与电路设计相关科研攻关项目，负责其中部分关键技术的研发，项目成果获2014年教育部技术发明一等奖、2015年国家技术发明二等奖。近年发表期刊会议论文十余篇，申请发明专利三十余项，其中12项已获授权。此外，作为指导老师获得2017全国大学生集成电路创新创业大赛全国总决赛优秀指导教师称号、2017全国大学生FPGA创新设计邀请赛企业特别奖、2018中国研究生创新实践系列大赛“华为杯”全国总决赛二等奖等竞赛奖项。

研究领域

1.低功耗集成电路设计 2.高能效智能计算电路设计

近期论文

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[1]Liu Bo, Qin Hai, Gong Yu, Ge Wei, Xia Mengwen and Shi Longxing, EERA-ASR: An Energy-Efficient Reconfigurable Architecture for Automatic Speech Recognition With Hybrid DNN and Approximate Computing, IEEE Access, vol. 6, 2018. [2]Wang Zhen, Xia Mengwen, Liu Bo (通信作者), Ruan Xing, Gong Yu, Yang Jinjiang, Ge Wei and Yang Jun, EERA-DNN: An energy-efficient reconfigurable architecture for DNNs with hybrid bit-width and logarithmic multiplier. IEICE Electronics Express, vol. 15, no. 8, 2018. [3]Liu Bo, Dong Wei, Xu Tingting, Gong Yu, Ge Wei, Yang Jinjiang and Shi Longxing, E-ERA: An Energy-Efficient Reconfigurable Architecture for RNNs Using Dynamically Adaptive Approximate Computing, IEICE Electronics Express, vol. 14, no. 15, 2017. [4]Cao Peng, Liu Bo, Yang Jinjiang, Yang Jun, Zhang Meng and Shi Longxing, Context Management Scheme Optimization of Coarse-grained Reconfigurable Architecture for Multimedia Applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 8, pp. 2321-2331, 2017. [5]Wang Chao, Cao Peng, Liu Bo and Yang Jun, Coarse-grained Reconfigurable Architecture with Hierarchical Context Cache Structure and Management Approach, IEICE Electronics Express, vol. 14, no. 6, 2017. [6]Liu Bo, Wang Xiaotong, Zhang Dongming and Ge Weiqi, Data Memory Structure and Management Strategy of Reconfigurable System for Radar, Journal of Shanghai Jiaotong University, vol. 51, no. 5, pp. 628-635, 2017.(inChinese) [7]Liu Bo, Ji Cheng, Zhu Wanyu and Mei Chen, Optimization of reconfigurable processor based on dynamic configuration context compression, Journal of Southeast University (Natural Science Edition), vol. 45, no. 5, pp. 822-827, 2015.(inChinese) [8]Liu Bo, Cao Peng, Zhu Min, Yang Jun, Liu Leibo, Wei Shaojun and Shi Longxing, Reconfiguration process optimization of dynamically coarse grain reconfigurable architecture for multimedia applications, IEICE Transactions on Information and Systems, vol. E95-D, no. 7, pp. 1858-1871, 2012.| [1]Liu Bo, Guo Shisheng, Qin Hai, Gong Yu, Yang Jinjiang, Ge Wei and Yang Jun, An Energy-efficient Reconfigurable Hybrid DNN Architecture for Speech Recognition with Approximate Computing, Accepted by 23rd IEEE Conference on DSP, 2018. [2]Liu Bo, Ruan Xing, Xia Mengwen, Gong Yu, Yang Jinjiang, Ge Wei and Yang Jun, An Energy-Efficient Accelerator for Hybrid Bit-width DNNs, IEEE Symposium Series on Computational Intelligence, pp. 1-8, Honolulu, HI, United states, February 2, 2018. [3]Gong Yu; Xu, Tingting, Liu Bo, Ge Wei, Yang Jinjiang, Yang Jun and Shi Longxing, Processing LSTM in memory using hybrid network expansion model, IEEE Workshop on Signal Processing Systems (SiPS), Lorient, France, November 14, 2017. [4]Xiao Jian, Liu Bo, A data cache optimization approach for coarse grain reconfigurable architecture for multimedia applications, IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB), December 16, 2016. [5]Liu Bo, Gong Yu, Wang Rui-He, Liu Yang, Performance-Conscious Reconfiguration Structure for Large-Scale Coarse-grained Reconfigurable System, 7th International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, pp. 354-359, October 26, 2015. [6]Liu Bo, Zhang Dong-Ming, Ge Wei-Qi and Gong Yu, A Novel Routing Structure of Coarse-Grained Reconfigurable Architecture for Radar Application, IEEE 11th International Conference on ASIC, (ASICON), July 21, 2016.