薛晓勇 - 复旦大学 - 微电子学院

个人简介

教育背景复旦大学，微电子学与固体电子学，博士承担及参与项目承担上海市科委和国家基金委多个项目，包括上海市自然科学基金、探索者计划、基金委青年项目、面上项目，参与多项国家重点项目与华为、中兴、智芯、中电科58所、中科院微电子所、之江实验室等公司机构开展创新研究项目论著参与编写3本存储器专著，在包括Nature Electronics、JSSC、ISSCC、IEDM、Symposium on VLSI、TCAS I & II、TVLSI等期刊或会议发表篇论文80余篇，获授权专利10余项教学及科创承担智能SOC设计、信号与系统、固态硬盘技术概论等课程的教学指导本科生参加腾飞计划、曦源计划，获2020年腾飞优胜杯指导学生参加全国大学生IC创新创业大赛，获得全国一等奖、二等奖及多项赛区奖

研究领域

存储器、存算一体电路与系统、近存计算

近期论文

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Xiaoyong Xue, Yarong Fu, Yanqing Zhao, etc., Dynamic Data-dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory, IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS II), vol. 64, no. 2, pp. 186-190, 2017 Jianguo Yang, Xiaoyong Xue, Juan Xu, etc., A self-adaptive write driver with fast termination of step-up pulse for ReRAM, IEICE Electronics Express (ELEX), vol. 13, no. 7, p. 20160195, 2016 Yufeng Xie, Xiaoyong Xue, Jianguo Yang, etc., A logic resistive memory chip for embedded key storage with physical security, IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS II), vol. 63, no. 4, pp. 336-340, 2016 X. Xue, J. Yang, Y. Lin*, etc., Low-Power Variation-Tolerant Nonvolatile Lookup Table Design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), vol. 24, no. 3, pp. 1174-1178, 2016 Xiaoyong Xue, Wenxiang Jian, Jianguo Yang, etc., A 0.13 μm 8 Mb Logic-Based CuxSiyO ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction, IEEE Journal of Solid-State Circuits (JSSC), vol. 48, no. 5, 2013