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Yongliang Zhang, Yitong Rong, Xuyang Duan, Zhen Yang, Qiang Li, Ziyu Guo, Xu Cheng, Xiaoyang Zeng, Jun Han, “An Energy-Efficient BNN Accelerator With Two-Stage Value Prediction for Sparse-Edge Gesture Recognition”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 1, pp. 320-333, Jan. 2024
Xuyang Duan, Yufan Chen, Menghan Li,Yitong Rong, Ruiqi Xie, Jun Han, “UArch: A Super-Resolution Processor With Heterogeneous Triple-Core Architecture for Workloads of U-Net Networks”, IEEE Transactions on Biomedical Circuits and Systems, vol. 17, no. 3, pp. 633-647, June 2023
Chao Fu, Li Wan, Jun Han, “LosaTM: A Hardware Transactional Memory Integrated With a Low-Overhead Scenario-Awareness Conflict Manager”, IEEE Transactions on Parallel and Distributed Systems, vol. 33, no. 12, pp. 4849-4862, 1 Dec. 2022
Yifan Zhao, Ruiqi Xie, Guozhu Xin, Jun Han, “A High-Performance Domain-Specific Processor With Matrix Extension of RISC-V for Module-LWE Applications”, IEEE Transactions on Circuits and Systems I: Regular Papers,vol. 69, no. 7, pp. 2871-2884, July 2022
Ruiqi Xie, Jun Yin, Jun Han, “DyGA: A Hardware-efficient Accelerator with Traffic-aware Dynamic Scheduling for Graph Convolutional Networks”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 12, pp. 5095-5107, Dec. 2021
Jun Yin, Jun Han, Ruiqi Xie, Chenghao Wang, Xuyang Duan, Yitong Rong, Xiaoyang Zeng, Jun Tao, “MC-LSTM: Real-time 3D Human Action Detection System for Intelligent Healthcare Applications”, IEEE Transactions on Biomedical Circuits and Systems, vol. 15, no. 2, pp. 259-269, Apr. 2021
Guozhu Xin, Jun Han, Tianyu Yin, Yuchao Zhou, Jianwei Yang, Xu Cheng, Xiaoyang Zeng, VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 8, pp. 2672-2684, Aug. 2020
Bingyi Zhang, Jun Han, Zhize Huang, Jianwei Yang, Xiaoyang Zeng, “A Real-time and Hardware-efficient Processor for Skeleton-based Action Recognition with Lightweight Convolutional Neural Network”, IEEE Transactions on Circuits and Systems II: Express Briefs, 66(12), pp. 2052-2056, Dec. 2019.
Jun Han, Yicheng Zhang, Shan Huang, Mengyuan Chen, Xiaoyang Zeng, “An Area-Efficient Error-Resilient Ultra-Low-Power Subthreshold ECG Processor”, IEEE Transactions on Circuits and Systems II: Express Briefs 63(10), pp 984-988, 2016/10
Jun Han, Renfeng Dou, Lingyun Zeng, Shuai Wang, Zhiyi Yu, Xiaoyang Zeng, A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation, IEEE Transactions on Circuits and Systems I: Regular Papers, 62(5), pp 1372-1381, 2015/5
Jun Han, Yang Li, Zhiyi Yu, Xiaoyang Zeng, A 65 nm Cryptographic Processor for High Speed Pairing Computation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(4), pp 692-701, 2015/4
Jun Han, Shuai Wang, Wei Huang, Zhiyi Yu, Xiaoyang Zeng, “Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(12), pp 2325-2330, 2013/12
Yao Zou, Jun Han, Sizhong Xuan, Shan Huang, Xinqian Weng, Dabin Fang, Xiaoyang Zeng, An Energy-Efficient Design for ECG Recording and R-Peak Detection Based on Wavelet Transform, IEEE Transactions on Circuits and Systems II: Express Briefs, , 62(2), pp 119-123, 2015/2
Gaowei Xu, Jun Han, Yao Zou, Xiaoyang Zeng, A 1.5-D Multi-Channel EEG Compression Algorithm Based on NLSPIHT, IEEE Signal Processing Letters, 22(8), pp 1118-1122, 2015/8
Renfeng Dou, Jun Han, Yifan Bo, Zhiyi Yu, Xiaoyang Zeng, “An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 22(11), pp 2245-2255, 2014/11
Zou Yao, Han Jun, Weng Xinqian, Zeng Xiaoyang, “An Ultra-Low Power QRS Complex Detection Algorithm Based on Down-Sampling Wavelet Transform”, IEEE Signal Processing Letters, 20(5), pp 515-518, 2013/5
Song Wang, Xu Cheng, Zi-Yu Guo, Jun Han, “A foreground digital calibration algorithm for time-interleaved ADCs with low computational complexity”, Microelectronics Journal, Vol. 136, 2023
Qiang Li, Jun Tao, Jun Han, “SPARK: An automatic Score-Power-Area efficient RISC-V processor microarchitecture SeeKer”, Microelectronics Journal, Vol. 132, 2023,
Fu Chao, Zhou Yuchao, Han Jun, “A hardware-efficient dual-source data replication and local broadcast mechanism in distributed shared caches”, Microelectronics Journal, vol. 118, December 2021
Zhang Yong-Liang, Li Qiang, Zhang Hui, Wang Wei-Zhen, Han Jun, Zeng Xiao-Yang, Cheng Xu, A 28nm, 397W real-time dynamic gesture recognition chip based on RISC-V processor, Microelectronics Journal, vol. 116, October 2021
Jianwei Yang, Fan Dai, Jielin Wang, Jianmin Zeng, Zhang Zhang, Jun Han, Xiaoyang Zeng, “Countering power analysis attacks by exploiting characteristics of multicore processors”, IEICE Electronics Express, Volume 15 (2018) Issue 7
Zhang Yuli, Han Jun, Weng Xinqian, He Zhongzhu, Zeng Xiaoyang, “Design approach and implementation of application specific instruction set processor for SHA-3 blake algorithm”, IEICE Transactions on Electronics, v E95-C, n 8,pp 1415-1426, August 2012
Zhou Weina, Dai Lin, Zou Yao, Zeng Xiaoyang, Han Jun, “A high speed reconfigurable face detection architecture based on adaboost cascade algorithm”, IEICE Transactions on Information and Systems, v E95-D, n 2, pp 383-391,February 2012
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