个人简介
科研/教育经历
1996-2000：西安微电子技术研究所，计算机系统结构，博士
1992-1995：西安电子科技大学，半导体器件与微电子学，硕士
1982-1986：哈尔滨工业大学，半导体物理与器件，学士
工作经历
2020-至今：北京大学，集成电路学院,研究员
2002-2020：北京大学，信息学院,副教授
2000-2002：清华大学，微电子研究所，博士后
1986-2000：西安微电子技术研究所，工程师
近期论文
查看导师新发文章
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1.Yinxuan Lyu, Jianhua Feng, Kai Zhu, Hongfei Ye, Dunshan Yu, Fully on-chip clock jitter and skew measurement scheme via incoherent subsampling, Microelectronics Journal, 2020, 96(2):1-10.
2.Yi Zhong, Jianhua Feng, Xiaoxin Cui, and Xiaole Cui, Machine Learning Aided Key-Guessing Attack Paradigm Against Logic Block Encryption, Journal of Computer Science and Technology, 2021, 36 (5): 1102-1117.
3.Jianhua Feng, Dunshan Yu, All-digital synchronous 2 × time-difference amplifier based on time register, Electronics Letters, 2017, 53(16):1102-1104.
4. Kai Zhu, Jianhua Feng, Yinxuan Lyu and Ai He, High-precision differential time integrator based on time adder, Electronics Letters, 2018, 54 (22): 1268-1270.
5. Haifeng Guo, Jianhua Feng, Yinxuan Lyu, Highly-linear wide-range voltage-controlled delay element with body bias technique, Microelectronics Journal, 2020, 96(2): 1-5.
6. Kai Zhu, Jianhua Feng, Yinxuan Lyu, A 336fsrms 0.89mW 200MS/s 5MHz Bandwidth 2–2 MASH ΔΣ Time-to-Digital Converter with Differential Time-Mode Arithmetic Units, IEEE International Symposium on Circuits and Systems (ISCAS), 2020.12-14, 1-5
7. Jianhua Feng, Linqi Shi, Weixin Gai, Dunshan Yu, A 108fsrms 0.45mW 100MS/s 1.25MHz bandwidth multi-bit ΔΣ time-to-digital converter with dynamic element matching, IEEE International Symposium on Circuits and Systems (ISCAS), 2018, 1-5.
8. Da Li, Lei Jin, Liang Yan, Xinlei Jia, Jianquan Jia, Jianhua Feng, Impact of low temperature on the TSG Vt shift during erase cycling of 3-D NAND Flash memory, IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), 2019, 1-3.
9.Chen Zhen, Feng Jianhua, Xiang Dong, Yin Boxue, Scan chain configuration based X-filling for low power and high quality testing, IET Computers and Digital Techniques, 2010，4（1）: 1-13.
10. Lin Teng, Feng Jianhua, Yu Dunshan, A novel interconnect testing scheme for Xilinx FPGAs, IEICE Transactions on Information and Systems, 2009,VOL.E92-D, NO.5,1197-1199.
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