倪熔华 - 复旦大学 - 微电子学院

个人简介

教育背景 2008年09月-2013年03月美国俄勒冈州立大学，电子与计算机工程，博士 2005年09月-2008年06月复旦大学，微电子学，硕士 2001年09月-2005年07月复旦大学，微电子学，学士工作经历 2020年11月-至今复旦大学，研究员，博士生导师 2013年04月-2020年10月三星半导体（美国），高级工程师、主任工程师、高级主任工程师

研究领域

模拟及射频集成电路设计，包括收发机(Transceiver)及时钟(PLL)电路设计高速接口电路（SerDes）设计模数/数模转换器(ADC/DAC)设计

近期论文

查看导师新发文章（温馨提示：请注意重名现象，建议点开原文通过作者单位确认）

J. Lee, S. Han, J. Lee, B. Kang, J. Bae, J. Jang, S. Oh, J. Chang, S. Kang, K. Son, H. Lim, D. Jeong, I. Jong, S. Baek, J. Lee, R. Ni, Y. Zuo, C. Yao, S. Heo, T. Cho, and I. Kang, “A sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS”, IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC), Vol.54, no.12, pp.3541-3552, 2019; W. Wu, C.W. Yao, K. Godbole, R. Ni, P. Chiang, Y. Han, Y. Zuo, A. Verma, I. Lu, S. Son, and T. Cho, “A 28-nm 75-fs(rms) Analog Fractional-N Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction”, IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC), Vol.54, no.5, pp.1254-1265, 2019; J. Lee, S. Han, J. Lee, B. Kang, J. Bae, J. Jang, S. Oh, S. Ahn, S. Kang, Q. Bui, K. Son, H. Lim, D. Jeong, R. Ni, Y. Zuo, I. Jong, C. Yao, S. Heo, T. Cho, and I. Kang, “A Sub-6GHz 5G New Radio RF Transceiver Supporting EN-DC with 3.15Gb/s DL and 1.27Gb/s UL in 14nm FinFET CMOS”, IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC), vol.62, pp.354-356, 2019; W. Wu, C. Yao, K. Godbole, R. Ni, P. Chiang, Y. Han, Y. Zuo, A. Verma, I. Lu, S. Son, and T. Cho, “A 5.5-7.3 GHz analog fractional-N sampling PLL in 28-nm CMOS with 75 fsrmsJitter and -249.7 dB FoM”, Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, vol.2018-June, pp.52-55, 2018; S. Ko, C. Yao, J. Lee, S. Han, D. Kwon, W. Loke, R.Ni, and T. Cho, “Digital PLL design challenges for cellular RFICs”, IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT), pp.232-234, 2017; C. Yao, R. Ni, C. Lau, W. Wu, K. Godbole, Y. Zuo, S. Ko, N. Kim, S. Han, I. Jo, J. Lee, J. Han, D. Kwon, C. Kim, S. Kim, S. Son, and T. Cho, “A 14-nm 0.14-ps(rms) Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration”, IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC), Vol.52, no.12, pp. 3446-3457, 2017; C. Yao, W. Loke, R. Ni, Y. Han, H. Li, K. Godbole, Y. Zuo, S. Ko, N. Kim, S. Han, I. Jo, J. Lee, J. Han, D. Kwon, C. Kim, S. Kim, S. Son, and T. Cho, “A 14nm Fractional-N Digital PLL with 0.14ps(rms) Jitter and-78dBc Fractional Spur for Cellular RFICs”, IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC), vol.60, pp.422-422, 2017; R. Ni, K. Mayaram, and T. Fiez, “A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with-76dBm sensitivity for high data rate wireless sensor networks”, IEEE Symposium on VLSI Circuits, Digest of Technical Papers (VLSI), 2014; R. Ni, K. Mayaram, and T. Fiez, “A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks”, IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC), Vol.48, no.5, pp.1250-1263, 2013; R. Ni, K. Mayaram, and T. Fiez, “A 2.4GHz Hybrid PPF Based BFSK Receiver with +/-180ppm Frequency Offset Tolerance for Wireless Sensor Networks”, IEEE Symposium on VLSI Circuits, Digest of Technical Papers (VLSI), pp.40-41, 2012; R. Ni, “Low Power Receivers for Wireless Sensor Networks”, Ph.D. Dissertation, Oregon State University, 2013; C. Yao, R. Ni, “System and Method for Fast-Converging Digital-to-Time Converter (DTC) Gain Calibration for DTC-based Analog Fractional-N Phase Lock Loop (PLL)”, U.S. Patent, US 2019/0212703 A1;