江文宁 - 复旦大学 - 芯片与系统前沿技术研究院

个人简介

复旦大学芯片与系统前沿技术研究院青年副研究员。2020年7月于澳门大学电机及电脑工程系获博士学位，2020年8月至2021年12月于澳门大学微电子研究院进行博后研究工作。主要研究方向为高性能模数转换器（ADC）、高速接口电路、脑机接口等方向。主持/参与国家自然科学基金青年项目、重点研发计划、上海市扬帆专项、复旦大学全国重重点项目以及企业合作等多项项目。在ISSCC、JSSC、TCAS-I、CICC、ASSCC等会议和期刊上发表多篇文章，担任JSSC、TCAS-I、TCAS-II等期刊的审稿人。

研究领域

模数转换器 Data Converter 模拟电路设计 Analog Circuits Chiplet高速互连接口High speed Die-to-Die interface

近期论文

查看导师最新文章（温馨提示：请注意重名现象，建议点开原文通过作者单位确认）

A Modified Two-Stage Cascaded Hybrid Converter with Reduced Conduction Loss, Self-Balanced Flying Capacitors and Simplified Interleaving PWM Chuang Wang;Wenning Jiang 2023 IEEE International Symposium on Circuits and Systems (ISCAS) A 10b 1.25GS/s Residue Post-Amplified Pipelined-SAR ADC with Supply-and-Temperature Stabilized Open-Loop Residue Amplifier Xinsheng Wang;Maosong Shi;Peizhe Li;Jianwei Liu;Zhangcheng Huang;Chixiao Chen;Wenning Jiang 2023 IEEE International Symposium on Circuits and Systems (ISCAS) A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration Jie Liao;Bo Jiao;Jinshan Zhang;Shiwei Liu;Hao Jiang;Jun Tao;Wenning Jiang;Qi Liu;Lihua Zhang;Haozhe Zhu;Chixiao Chen 2023 IEEE International Symposium on Circuits and Systems (ISCAS) A Modified Interleaving Resonant Switched Capacitor Converter with Reduced Output Resistance and In-Situ Startup Chuang Wang;Wenning Jiang 2023 IEEE International Symposium on Circuits and Systems (ISCAS) A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier Wenning Jiang;Yan Zhu;Chixiao Chen;Hao Xu;Qi Liu;Ming Liu;Rui P. Martins;Chi-Hang Chan IEEE Journal of Solid-State Circuits 16.2 A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine Shiwei Liu;Peizhe Li;Jinshan Zhang;Yunzhengmao Wang;Haozhe Zhu;Wenning Jiang;Shan Tang;Chixiao Chen;Qi Liu;Ming Liu 2023 IEEE International Solid-State Circuits Conference (ISSCC) A Single-Channel 14b 500 MS/s Pipelined-SAR ADC with Reference Ripple Mitigation Techniques and Adaptive-Biased Floating Inverter Amplifier Wenning Jiang;Yan Zhu;Chi-Hang Chan;Rui Martins 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC) A 8.5 fJ/Addition Dynamic Analog 8-3 Compressor for Energy Efficient Computing-in-Memory Macros Peizhe Li;Jinshan Zhang;Wenning Jiang;Chixiao Chen 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion Danfeng Zhai;Wenning Jiang;Xinru Jia;Jingchao Lan;Mingqiang Guo;Sai-Weng Sin;Fan Ye;Qi Liu;Junyan Ren;Chixiao Chen IEEE Transactions on Circuits and Systems I: Regular Papers A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler Wenning Jiang;Yan Zhu;Chi-Hang Chan;Boris Murmann;Rui Paulo Martins IEEE Transactions on Circuits and Systems I: Regular Papers A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier Wenning Jiang;Yan Zhu;Minglei Zhang;Chi-Hang Chan;Rui Paulo Martins IEEE Journal of Solid-State Circuits 3.2 A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier Wenning Jiang;Yan Zhu;Minglei Zhang;Chi-Hang Chan;Rui P. Martins 2019 IEEE International Solid-State Circuits Conference - (ISSCC) A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler Wenning Jiang;Yan Zhu;Chi-Hang Chan;Boris Murmann;Seng-Pan U;Rui Paulo Martins 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC)