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Xu He, Sheqin Dong, Yuchun Ma, Signal Through-the-Silicon Via Planning and Pin Assignment for Thermal and Wire Length Optimization in 3D ICs, Integration, the VLSI Journal. 2010
Bei Yu(*), Sheqin Dong, et al, Voltage and Level-Shifter Assignment Driven Floorplanning，IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences,Vol. E92-A, No.12, Dec.2009
Yaoguang Wei, Sheqin Dong, Xianlong Hong, APWL-Y:an accurate and efficient wirelength estimation technique for hexagon/triangle placement, Integration, the VLSI Journal, Integration, the VLSI Journal, 40 (2007), p406-419
Chen S, Dong SQ, Hong XL, Yici Cai, Chung-Kuan Cheng, Jun Gu, “VLSI block placement with alignment constraints”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS 53 (8): 622-626 AUG 2006
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu, “An Integrated Floorplanning with an Efficient Buffer Planning Algorithm”, IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 24 (No. 4) (2005)
Xianlong Hong, Sheqin Dong, Gang Huang, Yici Cai, C.K. Cheng, Jun Gu, “Non-slicing Floorplan and Placement using Corner Block List Topological Representation”, IEEE Transaction on CAS, Vol. 51 (No. 5) (2004), pp228-233
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu, “Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks”, ACM Transactions on Design Automation of Electronic Systems, Vol. 9 (No. 2) (2004), p199-211
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu, “Floorplanning with Abutment Constraints Based on Corner Block List”, Integration, the VLSI Journal, Vol. 31 (No. 1) (2001), p65-77
Sheqin Dong, Xianlong Hong, Song Chen, Xing Qi, Ruijie Wang, “VLSI Module Placement with Preplaced Modules and Considering Congestion Using Solution Space Smoothing”, IEICE Transactions on Fundamental of Electronics, Communications and Computer Science, Vol. E86-A, (No.12) (2003), pp3136-3147
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu, “VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation”, IEICE Transactions on Fundamental of Electronics, Communications and Computer Science, Vol. E84A (No. 11) (2001), p2697-2704
Bei Yu, Sheqin Dong, et al, Floorplanning and Topology Generation for Application-Specific Network-on-Chip，ACM/IEEE ASP-DAC 2010,
Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, C.K.Cheng, Bus Via Reduction Based on Floorplan Revising, ACM/IEEE GLSVLSI Rhode Island, USA,May 16-18, 2010
Tao Lin, Sheqin Dong, Bei Yu, Song Chen, Satoshi Goto, A Revisit to Voltage Partitioning Problem, ACM/IEEE GLSVLSI Rhode Island, USA,May 16-18, 2010
Wentao Sui, Sheqin Dong, Jinian Bian, Wirelength-Driven Force-Directed 3D FPGA Placement,ACM/IEEE GLSVLSI Rhode Island, USA,May 16-18, 2010
Wenxu Sheng, Sheqin Dong, Yuliang Wu, Satoshi Goto, Fixed Outline Multi-Bend Bus Driven Floorplanning,ACM/IEEE ISQED 2010, USA,
Xu He, Sheqin Dong,Simultaneous Buffer and Interlayer Via Planning for 3D Floorplanning, ACM/IEEE ISQED 2009, USA, pp740-745
Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, C.K. Cheng, A Novel Fixed outline Floorplanner with Zero Deadspace for Hierarchical Design, ACM/IEEE International conference on CAD, 2008, USA,pp16-23
Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang (Tsinghua Univ., China), Satoshi Goto (Waseda Univ., Japan), Symmetry Constraint based on Mismatch Analysis for Analog Layout in SOI Technology, The 13th IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC2008), Korean, January,2008
Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong, “Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation” The 12th IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC2007), Yokohama, Japan, 2007.1
Hongjie Bai, Sheqin Dong, Xianlong Hong, Congestion driven buffer planning for X-Architecture, ACM/IEEE ISQED 2007, USA,pp835-840
Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto, “Fast Custom Instruction Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design”, IEICE Trans. Fundamentals, Vol. E91-A, No.6, pp. 1478-1487, June 2008.
Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto, “Exploring Partitions based on Search Space Smoothing for Heterogeneous Multiprocessor System”, IEICE Trans. Fundamentals, Special Section on Nonlinear Theory and its Applications, Vol. E91-A, No.6, pp.2456-2464, Sep.2008.
Hong Xianlong, Ma Yuchun, Dong Sheqin, Cai Yici, C.K. Cheng, Jun Gu, “A Floorplanning Representation Corner Block List and The Corner Block List Based Floorplanning Algorithm with Boundary Constraint”, SCIENCE IN CHINA (Series F), Vol. 47 (No. 1) (2004), p1-19
Song Chen, X. Hong, S. Dong, Y. Ma, Y. Cai, C.K. Cheng, J. Gu, “A Buffer Planning Algorithm for Chip-Level Floorplanning”, SCIENCE IN CHINA SERIES F-INFORMATION SCIENCES 47 (6): 763-776 DEC 2004
Yuchun Ma, Xianlong Hong, Sheqin Dong, C.K.Cheng, Jun Gu, “General Floorplans with L/T-shaped blocks using corner block list”, Journal of Computer Science and Technology vol.21, no. 6, Nov,2006 pp.922-926
Dong Sheqin, Hong Xianlong, Wu Youliang, Gu Jun, “Deterministic VLSI Block Placement Algorithm Using Less Flexibility First Principle”, Journal of Computer Science and Technology (JCST), Vol. 18 (No. 6) (2003), p739-746
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, C-K Cheng, Jun Gu, “Fast Evaluation of Bounded Slice-line Grid”, Journal of Computer Science and Technology (JCST), Vol. 19 (No. 6) (2004), p973-980
Sheqin Dong, Shuo Zhou, Xianlong Hong, Chungkuan Cheng, Jun Gu, Yici Cai, “An Optimum Placement Search Algorithm Based on Extended Corner Block List”, Journal of Computer Science and Technology (JCST), Vol. 17 (No. 6) (2002), p699-707
Di Long; Xianlong Hong; Sheqin Dong;“Signal-path driven partition and placement for analog circuit” Design Automation, 2006. Asia and South Pacific Conference on 24-27 Jan. 2006 Page(s):6
Renshen WANG, Sheqin DONG Xianlong HONG, “An Improved P-admissible Floorplan Representation Based on Corner Block List”, 2005.1, The 10th IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC2005), Shanghai, China, p1115-1118
Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu, “LFF Algorithm for Heterogeneous FPGA Floorplanning”, 2005.1, The 10th IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC2005), Shanghai, China, p1123-1126
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, C-K Cheng, Jun Gu, “An Integrated Floorplanning with an Efficient Buffer Planning Algorithm”, 2003.3, ACM/SIGDA International Symposium on Physical Design, USA
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, C-K Cheng, Jun Gu, “Dynamic Global Buffer Planning Optimization Based on Detail Block Locating and Congestion Analysis”, 2003.6, IEEE/ACM 40th Design Automation Conference, Los Angeles, USA, p 806-811
Shuo Zhou, Sheqin Dong, Xianlong Hong,Yici Cai, C-K Cheng, Jun Gu, “ECBL: An Extended Corner Block List with Solution Space including Optimum Placement”, 2001.3, ACM/SIGDA International Symposium on Physical Design, USA, pp150-155
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, C-K Cheng, Jun Gu, “Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List”, 2001.6, IEEE/ACM 38th Design Automation Conference, Las Vegas, USA, p770-775
Xianlong Hong, Gamg Huang, Yici Cai, Sheqin Dong, Jiangchun Gu, C.K. Cheng, Jun Gu, “Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan”, 2000.11.5, IEEE/ACM International Conference on CAD, p8-12
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