贾海昆 - 清华大学 - 集成电路学院

个人简介

贾海昆，博士，清华大学集成电路学院副教授、特别研究员和博士生导师。2009-2015年从清华大学微纳电子系获得学士和博士学位；2015-2016年在香港科技大学从事博士后研究工作；2016至2019年在硅谷创业公司从事高速串口设计工作；2019年12月入职清华大学集成电路学院。主要研究方向为硅基毫米波/太赫兹集成电路设计以及高速串行接口技术，包括：高性能硅基太赫兹信号源、毫米波高速无线通信收发机阵列、低功耗混合信号基带解调技术、毫米波FMCW雷达、大规模毫米波相控阵等等。作为负责人承担科技部重点研发计划课题、国家自然科学基金等科研项目。发表学术期刊和国际学术会议论文80多篇，包括集成电路设计领域顶级期刊JSSC、IEEE Trans. MTT、IEEE TCAS-I、国际固态电路会议ISSCC、欧洲固态电路会议ESSCIRC和亚洲固态电路会议A-SSCC等。

研究领域

射频、毫米波和太赫兹无线通信芯片设计大规模毫米波相控阵芯片与系统高速串行接口技术及其应用

近期论文

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H. Jia, W. Deng, P. Guan, Z. Wang, and B. Chi, “A 60 GHz 186.5 dBc/Hz FOM Quad-Core Fundamental VCO using Circular-Triple-Coupled-Transformer with No Mode Ambiguity in 65nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2021. D. Xu, Y. Kou, P. Lai, Z. Cheng, T. Y. Cheung, L. Moser, Y. Zhang, X. Liu, M. P. Lam, H. Jia, Q. Pan, W. H. Szeto, C. F. Tang, K. F. Mak, K. Sarfraz, T. Zhu, M. Kwan, E. Au, C. Conroy, K. K. Chan, “A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2021. P. Guan, *H. Jia, W. Deng, Z. Wang, B. Chi, ” An Ultra-Compact 16-to-45 GHz Power Amplifier within A Single Inductor Footprint Using Folded Transformer Technique,” IEEE Custom Integrated Circuits Conference (CICC), Jun. 2021. W. Deng, *H. Jia, R. Wu, S. Sun, C. Li, Z. Wang, B. Chi, “An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator” IEEE Custom Integrated Circuits Conference (CICC), Jun. 2021. W. Deng, Z. Song, R. Ma, J. Lin, J. Ye, S. Kong, S. Hu, H. Jia, and B. Chi, "An Energy-Efficient 10-Gb/s CMOS Millimeter-Wave Transceiver with Direct-Modulation Digital Transmitter and I/Q Phase-Coupled Frequency Synthesizer," IEEE Journal of Solid-State Circuits (JSSC), Vol. 55, No. 8, pp. 2027-2042, Aug. 2020. H. Jia, C. Prawoto, B. Chi, Z. Wang, and C.P. Yue, “A Full Ka-Band Power Amplifier with 32.9% PAE and 15.3 dBm Power in 65nm CMOS,” IEEE Trans. Circuits and Syst. I: Reg. Paper, vol. 65, no. 9, Sep. 2018, pp. 2657-2668. H. Jia, L. Kuang, W. Zhu, Z. Wang, F. Ma, Z. Wang, and B. Chi, “A 77 GHz Frequency Doubling Two-Path Phased-Array FMCW Transceiver for Automotive Radar,” IEEE J. Solid-State Circuits, vol.51, no. 10, Nov. 2016, pp. 2299-2311. H. Jia, L. Kuang, Z. Wang, and B. Chi, “A W-Band Injection-Locked Frequency Doubler Based on Top-Injected Coupled Resonator,” IEEE Trans. on Microw. Theory and Techn., vol. 64, no. 1, pp. 210-218, Jan. 2016. H. Jia, B. Chi, L. Kuang, and Z. Wang, “A 47.6-to-71.0 GHz 65nm CMOS VCO Based on Magnetically Coupled pi-Type LC Network,” IEEE Trans. on Microw. Theory and Techn., vol. 63, no. 5, pp. 1645-1657, May 2015. H. Jia, B. Chi, L. Kuang, and Z. Wang, “A W-Band Power Amplifier Utilizing a Miniaturized Marchand Balun Combiner,” IEEE Trans. Microw. Theory and Techn., vol. 63, no. 2, pp. 719-725, Feb. 2015. H. Jia, B. Chi, L. Kuang, and Z. Wang, “A Simple and Robust Self-Healing Technique for Millimeter-Wave Amplifiers,” IET Circuits Devices and Systems, vol. 10, no. 1, pp. 37-43, 2016. H. Jia, B. Chi, L. Kuang, and Z. Wang, “A 38-40 GHz Current-Reused Active Phase Shifter Based on Coupled Resonator,” IEEE Trans. Circuits and Syst. II: Express Briefs, vol. 61, no. 12, pp. 917-921, Dec. 2014. L. Kuang, B. Chi, H. Jia, et al., “Co-Design of 60GHz Wideband Front-End IC with On-Chip T/R Switch Based on Passive Macro-Modeling,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 11, pp. 2743-2754, Dec. 2014. L. Kuang, B. Chi, X. Yu, H. Jia, L. Chen, W. Zhu, M. Wei, Z. Song, and Z. Wang, “A Fully-Integrated 60 GHz 5 Gb/s QPSK Transceiver with T/R Switch in 65nm CMOS,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 12, pp. 3131-3145, Dec. 2014. H. Jia, B. Chi, and Z. Wang, “An 8.2 GHz Low-Phase-Noise Class F QVCO using Triple Coupling Technique in 65nm CMOS,” IEEE Europe Solid-State Circuit Conf. (ESSCIRC), pp. 124-127, Sep. 2015 Z. Huang, H. C Luong, B. Chi, Z. Wang, and H. Jia, “A 70.5-to-85.5 GHz 65nm phase-locked loop with passive scaling of loop filter,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Techn. Papers, Feb. 2015, pp. 1-3.