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Rui Xu, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Yuhong Song, Han Wang, Liang Shi Optimizing Data Placement for Hybrid SRAM+Racetrack Memory SPM in Embedded Systems TCAD 2023
(Referred Journal Publications)
“BOSS: An Efficient Data Distribution Strategy for Object Storage Systems with Hybrid Devices”. In IEEE Access, vol. 5, pp. 23979-23993, Sept. 2017. (SCI Indexed, JCR Q1)
“Refinery Swap: An Efficient Swap Mechanism for Hybrid DRAM-NVM Systems”. Future Generation Computer Systems (FGCS), 2017, 77:52-64. (SCI Indexed, JCR Q1)
"Towards the Design of Efficient and Consistent Index Structure with Minimal Write Activities for Non-Volatile Memory," in IEEE Transactions on Computers (TC), vol. 67, no. 3, pp. 432-448, Mar. 2018. (SCI Indexed, JCR Q1)
"Synthesizing Distributed Pipelining Systems with Timing Constraints via Optimal Functional Unit Assignment and Communication Selection," Journal of Computational Science (JOCS), 2017. (SCI Indexed)
"Optimal Functional-Unit Assignment for Heterogeneous Systems under Timing Constraint," IEEE Transactions on Parallel and Distributed Systems (TPDS), Volume: 28, Issue: 9, 2017. (SCI Indexed, JCR Q1)
"Efficient Assignment Algorithms to Minimize Operation Cost for Supply Chain Networks in Agile Manufacturing," in Computers & Industrial Engineering (CAIE), Volume: 108, 2017. (SCI Indexed, JCR Q2)
基于非易失性内存的持久化嵌入式内存数据库. 软件学报, 2016, 27(S2):320-327.
“A Unified Framework for Designing High Performance In-memory and Hybrid Memory File Systems”. Journal of Systems Architecture (JSA), vol. 68, pp. 51-64 Aug. 2016. (SCI Indexed, JCR Q2)
“A New Design of In-Memory File System Based on File Virtual Address Framework,” in IEEE Transactions on Computers (IEEE TC), Vol. 65, No. 10, pp. 2959-2972, Oct. 2016, Received the Honor of Editor’s Pick of the Year of 2016. (SCI Indexed, JCR Q1)
“Synthesizing Distributed Pipelining Systems with Timing Constraints via Optimal Functional Unit Assignment and Communication Selection,” in Journal of Computational Science, Mar. 2017. (SCI Indexed)
“Optimal Functional-Unit Assignment for Heterogeneous Systems under Timing Constraint,” in IEEE Transactions on Parallel and Distributed Systems, Mar. 2017. DOI:10.1109/TPDS.2017.2676764. (SCI Indexed, JCR Q1)
“FoToNoC: A Folded Torus-Like Network-on-Chip based Many-Core Systems-on-Chip in the Dark Silicon Era,” in IEEE Transactions on Parallel and Distributed Systems, Dec. 2016. DOI:10.1109/TPDS.2016.2643669. (SCI Indexed, JCR Q1)
“Design of Persistent Embedded Main Memory Databases on Non-Volatile Memory,” in 软件学报, Journal of Software, 2016, 27 (Suppl.2), pp. 320-327 (in Chinese). (EI Indexed)
“Morphable Resistive Memory Optimization for Mobile Virtualization”. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (IEEE TCAD), Vol. 35, No. 6, pp. 891-904, Jun. 2016(SCI Indexed, JCR Q2)
“A Compiler Assisted Wear Leveling for Morphable PCM in Embedded Systems,” in Journal of Systems Architecture (JSA), 2016. doi: 10.1016/j.sysarc.2016.06.007. (SCI Indexed, JCR Q2)
“Write Reconstruction for Write Throughput Improvement on MLC PCM based Main Memory,” in Journal of Systems Architecture (JSA), 2016. (SCI Indexed) doi:10.1016/j.sysarc.2016.05.006(SCI Indexed, JCR Q2)
“Data Allocation with Minimum Cost under Guaranteed Probability for Multiple Types of Memories,” in Journal of Signal Processing Systems (JSPS), Volume 84, Issue 1, pp 151-162, July 2016. (SCI Indexed, JCR Q4)
“Properties of Self-Timed Ring Architectures for Deadlock-Free and Consistent Configuration Reaching Maximum Throughput,” in Journal of Signal Processing Systems (JSPS), Volume 84, Issue 1, pp 123-137, July 2016. (SCI Indexed, JCR Q4)
“Efficient Data Placement for Improving Data Access Performance on Domain Wall Memory,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (IEEE TVLSI), 2016. (SCI Indexed, JCR Q2)
“A Time, Energy, and Area Efficient Domain Wall Memory based SPM for Embedded Systems,” in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (IEEE TCAD), 2016. (SCI Indexed, JCR Q2)
“Reliability-Guaranteed Task Assignment and Scheduling for Heterogeneous Multiprocessors Considering Timing Constraint”, published in Journal of Signal Processing Systems (JSPS), Vol. 81, Issue 3, pp. 359-375, Dec. 2015. (SCI Indexed, JCR Q4)
"Optimizing Task and Data Assignment on Multi-Core Systems with Multi-Port SPMs," published in IEEE Transactions on Parallel and Distributed Systems (TPDS), Vol. 26, No. 9, pp.2549-2560, Sept. 2015 (SCI Indexed, JCR Q1)
(Referred Conference Papers)
"On the Design of Minimal-Cost Pipeline Systems Satisfying Hard/Soft Real-Time Constraints," IEEE International Conference on Computer Design (ICCD), Boston, MA, USA, Nov. 2017. (THE BEST PAPER AWARD)
“UDORN: A Design Framework of Persistent In-Memory Key-value Database for NVM”. In Proceedings of IEEE Non-volatile Memory System & Applications Symposium (NVMSA), Hsinchu, Taiwan, China, Aug. 2017.
“减少多表连接对非易失性存储器写操作的研究”，in the 15th CCF Annual Conference on Embedded Systems (ESTC 2017), Shenyang, China, Nov. 2017.（The Best Student Paper Award）
“Optimizing Data Placement of MapReduce on Ceph-Based Framework under Load-Balancing Constraint,” Proc. International Conference on Parallel and Distributed Systems (ICPADS), Wuhan, China, Dec. 2016
“Performance Optimization for In-Memory File Systems on NUMA Machines,” Proc. 17th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT), Guangzhou, China, Dec. 2016.
“Optimal Functional Assignment and Communication Selection under Timing Constraint for Self-Timed Pipelines,” Proc. 13th International Conference of Embedded Software and System (ICESS), Chengdu, China, Aug. 2016.
“The Design and Implementation of an Efficient Data Consistency Mechanism for In-Memory File Systems,” Proc. 13th International Conference of Embedded Software and System (ICESS), Chengdu, China, Aug. 2016.
“The Design and Implementation of a High-Performance Hybrid Memory File System,” Proc. International Conference on Advanced Cloud and Big Data (CBD), Chengdu, China, Aug. 2016.
“The Design of an Efficient Swap Mechanism for Hybrid DRAM-NVM Systems,” Proc. International Conference on Embedded Software (EMSOFT), Pittsburgh, PA, USA, Oct. 2016.
“Optimal Functional-Unit Assignment and Buffer Placement for Probabilistic Pipelines,” Proc. International Conference on Hardware/Software Co-design and System Synthesis (CODES+ISSS), Pittsburgh, PA, USA, Oct. 2016.、
“Access Characteristic Guided Read and Write Cost Regulation for Performance Improvement on Flash Memory,” Proc. 14th USENIX Conference on File and Storage Technologies (FAST 2016), Santa Clara, USA, Feb. 2016.
“Designing an Efficient Persistent In-Memory File System,” Proc. the 4th IEEE Non-Volatile Memory System and Applications Symposium (NVMSA), Hongkong, Aug. 2015. (THE BEST PAPER AWARD)
"Area and Performance Co-Optimization for Domain Wall Memory in Application-Specific Embedded Systems," in Proc. of the 52nd Design Automation Conference (DAC 2015), San Francisco, CA, USA, Jun. 2015, pp.20:1-20:6.
"Optimizing Data Placement for Reducing Shift Operations on Domain Wall Memories," in Proc. of the 52nd Design Automation Conference (DAC 2015), San Francisco, CA, USA, Jun. 2015, pp.139:1-139:6.
"Maximizing IO Performance via Conflict Reduction for Flash Memory Storage Systems," in Proc. of the 18th International Conference on Design, Automation, and Test in Europe (DATE 2015), Grenoble, France, March 2015.
"nCode, Limiting Harmful Writes to Emerging Mobile NVRAM through Code Swapping, " in Proc. of the 18th International Conference on Design, Automation, and Test in Europe (DATE 2015), Grenoble, France, March 2015.
"On the Design of High-Performance and Energy-Efficient Probabilistic Self-Timed Systems," in Proc. of the 17th IEEE International Conference on High Performance Computing and Communications (HPCC/CSS/ICESS 2015), New York, USA, Aug. 2015, pp: 260-265.
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