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研討會論文
C.J. Huang, C.J. Wu, H.A. Teng, and K.N. Chiang, "Research on Multi-Scale Structural Analysis using the Atomistic-Continuum Equivalent Mechanics," CSWNST-8, Hong Kong, Dec. 19-22, 2010.
S. Y. Syu, T. Y. Hung, C. J. Huang, H. J. Wang, H. L. Lee and K.N. Chiang, "Reliability Assessment of 3D Chip Stacking Package Using Metal Bonding and Through Silicon Via Technologies," ASME International Mechanical Engineering Congress & Exposition (IMECE), Vancouver, Canada, Nov. 12-18, 2010.
C.J. Huang, C.J. Wu, H.A. Teng, and K.N. Chiang, "Carbon Nanotubes Structural Mechanics Using the Atomistic-Continuum Mechanics and Equivalent Methods," ACCM-7, Taipei, Taiwan, Nov. 15-18, 2010.
S. Y. Yang, T. L. Chou, C. F. Huang, C. J. Wu, C. L. Hsu, and K. N. Chiang "Strength Determination of Light-emitting diodes and Chip Structure Design," IMPACT2010, Taipei, Taiwan, Oct 20-22, 2010.
N. Y. Wang, S. Y. Chiang, T. L. Chou and K. N. Chiang, "Life Prediction of High Concentration Photovoltaic Modules Subjected to Thermal Cycling Test," IMPACT2010,
Taipei, Taiwan, Oct. 20-22.
S. Y. Yang, T. L. Chou, C. F. Huang, C. J. Wu, C. L. Hsu, and K. N. Chiang "Determination of Maximum Strength and Optimization of LED Chip Structure," ESTC2010, Berlin, Germany, Sep 14-16, 2010
Yen-Fu Su, Tuan-Yu Hung, Shin-Yueh Yang, and Kuo-Ning Chiang, "A Study on the Thermal Performance of a Chip-in-substrate-type LED Package Structure" ICSJ2010, Tokyo, Japan, August 24-26, 2010.
Ning-Yuan Wang, Shih-Ying Chiang, Tsung-Lin Chou, Zun-Hao Shih, Hwen-Fen Hong and Kuo-Ning Chiang, "Transient Thermal Analysis of High-Concentration Photovoltaic Cell Module Subjected to Coupled Thermal and Power Cycling Test Conditions," Itherm2010, Las Vegas, Nevada, USA, June 2-5, 2010.
T. Y. Hung, S. Y. Chiang, C. Y. Chou, C. C. Chiu, and K. N. Chiang, "Thermal Design and Transient Analysis of Insulated Gate Bipolar Transistors of Power Module," ITherm 2010, Las Vegas, USA, June 2-5, 2010.
S. Y. Chiang, T. Y. Hung, Ray Hsing and K. N. Chiang, "Temperature Dependent Current Crowding Analysis of Insulated Gate Bipolar Transistor," ICEP2010, Sapporo, Hokkaido, Japan, May 12-14, 2010.
C. J. Wu, M. C. Hsieh, and K. N. Chiang, "Delamination Investigation of Copper Bumps in 3D Chip Stacking Packages Using the Modified Virtual Crack Closure Technique," ICEP 2010, Sapporo, Japan, May 12-14, 2010.
Shih-Ying Chiang, Tsung-Lin Chou, Hwen-Fen Hong and Kou-Ning Chiang, "Life Prediction of HCPV Under Thermal Cycling Test Condition," MAM2010, Mechelen, Belgium, Mar 7-10, 2010.
C. J. Wu, M. C. Hsieh, C. C. Chiu, M. C. Yew, and K. N. Chiang "Interfacial Delamination Investigation between Copper Bumps in 3D Chip Stacking Package by Using the Modified Virtual Crack Closure Technique," MAM 2010, Mechelen, Belgium, Mar. 7-10, 2010.
Y. F. Su, S. Y. Yang, W. H. Chi and K. N. Chiang, "Light Degradation Prediction of High Power Light Emitting Diode Lighting Modules,"EuroSimE2010, Bordeaux, France, Apr. 26-28, 2010.
H. H. Chang, J. H. Huang, C. W. Chiang, Z. C. Hsiao, H. C. Fu, Y. H. Chen and K. N. Chiang, “Process Integration for 3D Chip Stacking with Thin Wafer Handling Technology,” in Materials for Advanced Metallization Conference, Mar. 7-10, Mechelen, Belgium, 2010.
Chao-Jen Huang, Chung-Jung Wu, Hung-An Teng, and Kuo-Ning Chiang "A Robust Nano-Mechanics Approach for Tensile and Modal Analysis Using Atomistic-Continuum Mechanics Method," ICONN 2010, Sydney, Australia, Feb 22-26, 2010.
Tsung-Lin Chou, Shin-Yueh Yang, and Kuo-Ning Chiang, “Overview and Applicability of Residual Stress Estimation of Film-Substrate Structure,” International Conference of Advanced Manufacturing, Feburary 2-5, 2010, Kenting, Taiwan.
H. A. Deng, S. Y. Yang, C. N. Han, T. L. Chou, and K. N. Chiang "Warpage Analysis of High Power InGaN Light Emitting Diodes after Laser Lift-off," EMAP 2009, Penang, Malaysia, Dec 1-3, 2009.
S. Y. Chiang, T. L. Chou, Z. H. Shih, H. F. Hong and K. N. Chiang "Non-Uniform Thickness Effect of Die Bonding Interface in High-Concentration Photovoltaic Module," EMAP 2009, Penang, Malaysia, Dec 1-3, 2009.
Shin-Yueh Yang, Shih-Ying Chiang, Chan-Yen Chou, Ming-Chih Yew, and Kuo-Ning Chiang, "Reliability Analysis of Copper Interconnections of System-in-Packaging," 4th IMPACT, Oct. 21-23, Taipei, Taiwan.2009.
Masafumi Sano, Chan-Yen Chou, Tuan-Yu Hung, Shin-Yueh Yang, Chao-Jen Huang, and Kuo-Ning Chiang, "Reliability and Parametric Study on Chip Scale Package Under Board-Level Drop Test," 4th IMPACT, Oct. 21-23, Taipei, Taiwan. 2009.
Tsung-Lin Chou, Chien-Fu Huang, Cheng-Nan Han, Shin-Yueh Yang, and Kuo-Ning Chiang, “Fabrication Process Simulation and Reliability Improvement of High- brightness LEDs,” 20th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF2009), October 5-9, 2009, Arcachon, France (All accepted contributions to the conference have been published as a special issue of Microelectronics Reliability.)
C. Y. Chou, C. J. Huang, M. Sano, and K. N. Chiang, "Metal trace impact life prediction model for stress buffer enhanced package," 17th European Microelectronics and Packaging Conference & Exhibition (EMPC2009), Rimini, Italy, June 15-18, 2009.
T. Y. Hung, M. C. Yew, C. Y. Chou, and K. N. Chiang, "A study of thermal performance for chip-in-substrate package on package," 17th European Microelectronics and Packaging Conference & Exhibition (EMPC2009), Rimini, Italy, June 15-18, 2009.
H. H. Chang, Y. C. Shih, Z. C. Hsiao, C. W. Chiang, Y. H. Chen and K. N. Chiang, "3D Stacked Chip Technology Using Bottom-up Electroplated TSVs",Electronic Components and Technology Conference (ECTC 2009), San Diego, California USA, May 26-29, 2009.
C. J. Wu, M. C. Hsieh, and K. N. Chiang, "Strength Evaluation of Silicon Die for 3D Chip Stacking Packages Using ABF as Dielectric and Barrier Layer in Through-Silicon Via,", Materials for Advanced Metallization Conference (MAM 2009), Grenoble, France, Mar. 8-11, 2009.
C. C. Chiu, C. J. Huang, S. Y. Yang, C. C. Lee, and K. N. Chiang, "Investigation of the Delamination Mechanism of the Thin Film Dielectric Structure in Flip Chip Packages" Materials for Advanced Metallization Conference (MAM 2009), Grenoble, France, Mar. 8-11, 2009.
Masafumi Sano, Chan-Yen Chou, Tuan-Yu Hung, Shin-Yueh Yang, Kuo-Ning Chiang, “Uncertainty and Reliability Analysis of Chip Scale Package Subjected to Board-level Drop Test”, International Conference on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE2009), Delft, Netherlands April 27-29, 2009.
C. J. Huang, C. Y. Chou, K. N. Chiang, “Dynamic Study and Structure Enhancement of Small Outline Dual-in-line Memory Module”, International Conference on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE2009), Delft, Netherlands April 27-29, 2009.
W. H. Chi, T. L. Chou, C. N. Han, S. Y. Yang, and K. N. Chiang, "Analysis of Thermal Performance for High Power Light Emitting Diodes Lighting Module", International Conference on Electronics Packaging (ICEP 2009),Kyoto, Japan, April 14-16, 2009
C. J. Wu, M. C. Hsieh, and K. N. Chiang, "Die-Cracking Evaluation of Silicon Chip Covered with Polymer Film for 3D Chip Stacking Packages," International Conference on Electronics Packaging, ICEP 2009, Kyoto, Japan, Apr. 14-16, 2009.
SCI期刊論文
W. H. Chi, T. L. Chou, C. N. Han, S. Y. Yang, and K. N. Chiang, “Analysis of Thermal and Luminous Performance of MR-16 LED Lighting Module,” IEEE Transactions on Components and Packaging Technologies, Vol. 33, Issue: 4, pp. 713-721, 2010.
C.C. Chiu, C.J. Huang, S.Y. Yang, C.C. Lee, and K.N. Chiang, "Investigation of the delamination mechanism of the thin film dielectric structure in flip chip packages," Microelectronic Engineering, vol. 87, pp. 496-500, 2010.
C.J. Wu, M.C. Hsieh, and K.N. Chiang, "Strength evaluation of silicon die for 3D chip stacking packages using ABF as dielectric and barrier layer in through-silicon via," Microelectronic Engineering, vol. 87, pp. 505-509, 2010.
C. C. Lee, C. C. Lee, and K. N. Chiang, “Electromigration Characteristic of SnAg3.0Cu0.5 Flip Chip Interconnection,” IEEE Trans. Adv. Packag, Vol. 33, Issue: 1, pp. 189-195, 2010.
C. Y. Chou, T. Y. Hung, C. J. Huang, and K. N. Chiang, “Development Of Empirical Equations For Metal Trace Failure Prediction Of Wafer Level Package Under Board Level Drop Test,” IEEE Trans. Adv. Packag, Vol. 33, Issue: 3, pp. 681-689, 2010.
C. J. Wu, M. C. Hsieh, C. C. Chiu, M. C. Yew, and K. N. Chiang, “Interfacial delamination investigation between copper bumps in 3D chip stacking package by using the modified virtual crack closure technique,” Microelectronic Engineering, in press, 2010.
Tsung-Lin Chou, Chen-Hung Chu, Hsin-Nan Chiang, and Kuo-Ning Chiang, “Residual Stress and Thermal Effect of MEMS Pressure Sensor,” Electronic Monthly,
Volume 168, pp. 150-167, July 2009. (in Chinese)
C. C. Lee, C. C. Chiu, C. C. Hsia, and K. N. Chiang, "Interfacial fracture analysis of CMOS Cu/Low-k BEOL interconnect in advanced packaging structures," IEEE
Transactions on Advanced Packaging, Vol. 32, No.1, pp. 53-61, 2009.
Tsung-Lin Chou, Chen-Hung Chu, Chun-Te Lin and Kuo-Ning Chiang, “Sensitivity analysis of packaging effect of silicon-based piezoresistive pressure sensor,” Sensors & Actuators: A. Physical, Volume 152, Issue 1, pp. 29-38, 2009.
Tzu-Sen Yang, Yujia Cui, Chien-Ming Wu, Jem-Mau Lo, Chi-Shiun Chiang,Wun-Yi Shu, Chung-Shan Yu, Kuo-Ning Chiang, and Ian C. Hsu, "Determining the Zero-Force Binding Energetics of Intercalated DNA Complex Using Single Molecule Approach," ChemPhysChem, 10, 2791-2794 2009.
Tsung-Lin Chou, Chien-Fu Huang, Cheng-Nan Han, Shin-Yueh Yang, and Kuo-Ning Chiang, “Fabrication Process Simulation and Reliability Improvement of High- brightness LEDs,” Microelectronics Reliability, Volume 49, Issue 9-11, pp. 1244-1249, 2009.
Ming-Chih Yew, Mars Tsai, Dyi-Chung Hu, Wen-Kun Yang, Kuo-Ning Chiang, "Reliability analysis of a novel fan-out type WLP," Soldering & Surface Mount Technology Volume 21(3): p. 30-38 , 2009.
C. J. Wu, C. Y. Chou, C. N. Han, and K. N. Chiang, "Estimation and Validation of Elastic Modulus of Carbon Nanotubes Using Nano-Scale Tensile and Vibrational Analysis," Computer Modeling in Engineering and Science, Vol. 41, No. 1, pp. 49-68, 2009.
M. C. Yew, C. C. A. Yuan, C. J. Wu, D. C. Hu, W. K. Yang, and Kuo-Ning Chiang, “Investigation of the Trace Line Failure Mechanism and Design of Flexible Wafer Level Packaging,” IEEE Transactions on Advanced Packaging, Volume, 32, No. 2, pp. 390-398, 2009.
H. T. Ku, and K. N. Chiang, "The mechanical stress resistance capability of stress buffer structures in analog devices," Microelectronic Reliability, Vol. 48, pp. 716-723, 2008.
C. C. Chiu, C. C. Lee, T. L. Chou, C. C. Hsia, and K. N. Chiang, "Analysis of Cu/Low-k structure under back end of line process," Microelectronic Engineering, Vol. 85, Issue 10, pp. 2150-2154, 2008.
C. C. Lee, T. L. Chou, C. C. Chiu, C. C. Hsia, and K. N. Chiang, "Cracking energy estimation of ultra low-k package using novel prediction approach combined with global–local modeling technique," Microelectronic Engineering, Vol. 85, Issue 10, pp. 2079-2084, 2008.
C. Y. Chou, T. Y. Hung, S. Y. Yang, M. C. Yew, W. K. Yang, and K. N. Chiang, "Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact," Microelectronics Reliability, Vol. 48, pp. 1149-1154, 2008.
Chang-Chun Lee, Tai-Chun Huang, Chin-Chiu Hsia, and Kuo-Ning Chiang, “Interfacial Fracture Investigation of Low-k Packaging Using J-Integral Methodology,” IEEE TRANSACTIONS ON ADVANCED PACKAGING, Vol. 31, pp. 91-99, 2008
K. N. Chiang, C. Y. Chou, C. J. Wu, C. J. Huang, and M. C. Yew, "Analytical solution for estimation of temperature-dependent material properties of metals using modified Morse potential," Computer Modeling in Engineering and Science, Vol. 37, pp. 85-96, 2008.
C. C. Lee, S. M. Chang and K. N. Chiang, “Sensitivity Design of DL-WLCSP Using DOE With Factorial Analysis Technology”, IEEE Transaction of Advanced Packaging, Vol 30, No. 1, pp. 44-55, April 2007.
C. A. Yuan, G. Q. Zhang, C. N. Han, and K. N. Chiang, "Numerical simulation on the mechanical characteristics of double-stranded DNA under axial stretching and lateral unzipping," J. Appl. Phys. 101, 074702, 2007.
C. C. Lee, H. C. Liu and K. N. Chiang, "3D Structure Design and Reliability Analysis of Wafer Level Package with Stress Buffer Mechanism," IEEE Transactions on Component and Packaging Technologies, Vol. 30, No.1, pp.110- 118, 2007.
C. C. Chiu, C. J. Wu, C. T. Peng, K. N. Chiang, T. Ku, and K. Cheng, "Failure life prediction and factorial design of lead-free flip chip package," Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers, Vol.30, No. 3, pp. 481-490, 2007.
S. M. Chang, C. Y. Cheng, L. C. Shen, K. N. Chiang, Y. J. Hwang, Y. F. Chen, C. T. Ko, and K. C. Chen, "A novel design structure for WLCSP with high reliability, low cost, and ease of fabrication," IEEE Transactions on Advanced Package, Vol. 30, No. 3, pp. 377-383, 2007.
C. T. Lin, and K. N. Chiang, "From atomic-level lattice structure to estimate the silicon mechanical bulk behavior using the atomistic-continuum mechanics," Key Engineering Materials, Vol 334-335 I, pp. 281-284, 2007
C. C. Chiu, H. H. Chang, C. C. Lee, C. C. Hsia, and K. N. Chiang, "Reliability of interfacial adhesion in a multi-level copper/low-k interconnect structure," Microelectronics Reliability, Vol. 47, pp. 1506-1511, 2007.
M. C. Yew, C. Y. Chou, and K. N. Chiang, "Reliability assessment for solders with a stress buffer layer using ball shear strength test and board-level finite element analysis." Microelectronics Reliability, Vol. 47, pp. 1658-1662, 2007.
C. C. Lee, C. C. Lee, H. T. Ku, S. M. Chang, and K. N. Chiang, "Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology," Microelectronics Reliability Vol. 47, pp. 196-204, 2007.
Ming-Chih Yew, Chien-Chia Chiu, Shu-Ming Chang and Kuo-Ning Chiang, "A Novel Crack and Delamination Protection Mechanism for a WLCSP Using Soft Joint
Technology," Soldering & Surface Mount Technology, Vol. 18, Issue 3, 2006, pp. 3-13.
K. N. Chiang , Chien Chen Lee, Chang Chun Lee and K. M. Chen, "Current crowding-induced electromigration in SnAg3.0Cu0.5 micro-bumps", Appl. Phys. Lett., 88, 072102, 2006.
K. N. Chiang , C.A. Yuan, C. N. Han, C. Y. Chou and Yujia Cui, "Mechanical Characteristic of ssDNA /dsDNA Molecule Under External Loading", Appl. Phy. Lett., 88, 023902, 2006
K. N. Chiang, C. Y. Chou, and C. J. Wu, and C. A. Yuan, "Prediction of The Bulk Elastic Constant of Metals Using Atomic-Level Single-Lattice Analytical Method" Appl. Phys. Lett. 88, 171904, 2006
Chen, KM, Houng, KH, Chiang, KN, "Thermal resistance analysis and validation of flip chip PBGA packages", MICROELECTRON RELIAB 46 (2-4): 440-448 FEB-APR 2006
Chang, KC, Chiang, KN, "Growth analysis of interfacial delamination in a plastic ball grid array package during solder reflow using the global-local finite element model", J STRAIN ANAL ENG 41 (1): 19-30 JAN 2006
Lee, C. C., Ku, H. T., Chiu, C. C., and Chiang, K. N., “A Novel Prediction Technique for Interfacial Crack Growth of Electronic Interconnect,” Key Engineering Materials, pp.533, 2006.
Liu, C. M., Lee, C. C., Ku, H. T., Chiu, C. C., and Chiang, K. N., “Interconnect Design and Thermal Stress/Strain Analysis of Flip Chip Packaging,” Key Engineering Materials, pp.521, 2006.
K. C. Chang and K. N. Chiang, "Growth Analysis of Interfacial Delamination of Plastic Ball Grid Array Package During Solder Reflow Using Global-Local Finite Element Method." Journal of Strain Analysis for Engineering Design, Vol. 41, No. 1, pp. 19-30, 2006.
M. C. Yew, C. Y. Chou, C. S. Huang, W. K. Yang, K. N. Chiang, "The Solder on Rubber (SOR) Interconnection Design and Its Reliability Assessment Based on Shear Strength Test and Finite Element Analysis," Journal of Microelectronics Reliability, Vol. 46, pp. 1874-1879, 2006
Liu, C. M., Lee, C. C., and Chiang, K. N., “Enhancing the Reliability of Wafer Level Packaging by Using Solder Joints Layout Design,” IEEE Transactions on Component and Packaging Technologies, Vol. 29, No. 4, pp. 877-885, 2006.
W. H. Chen, S. R. Lin and K. N. Chiang, "Predicting the Liquid Formation for the Solder Joints in Flip Chip Technology", ASME Transactions Journal of Electronic Packaging, Vol. 128, No. 4, pp. 331-338, 2006.
C. C. Lee, C. T. Peng, and K. N. Chiang, "Packaging Effect Investigation of CMOS Compatible Pressure Sensor Using Flip Chip and Flex Circuit Board Technologies,” Sensors and Actuators Journal A, Vol 126/1, pp 48-55, 2006.
Kuo-Ming Chen, J.D. Wu and Kuo-Ning Chiang, "Effects of Pre-Bump Probing and Bumping Processes on Eutectic Solder Bump Electromigration", Microelectronics and Reliability, In Press, Corrected Proof, Available online 28 February 2006.
K. M. Chen and K. N. Chiang, "Developing an Analytic Methodology to Accurately Predict Probing Depth in Integrated Circuit Structures", Journal of Electronic Materials, Vol. 35, pp.257-265, 2006.
C. C. Lee, and K. N. Chiang, “Design and Reliability Analysis of a Novel Wafer Level Package with Stress Buffer Mechanism,” Journal of the Chinese Institute of Engineers, Vol. 29, No. 3, pp. 433-443, May 2006.
K. N. Chiang, C. H. Chang and C. T. Peng, "Local-Strain Effects in Si/SiGe/Si Islands on Oxide". Appl. Phys. Lett, 87, 191901, 2005.