邓伟 - 清华大学 - 集成电路学院

个人简介

2002-2009年在电子科技大学电子工程系并先后获得学士和硕士学位；2009-2014年在日本东京工业大学（Tokyo Institute of Technology）先后获得博士学位和从事博士后研究；2015-2019年在美国苹果公司（Apple Inc.）总部任高级主任工程师，面向无线通信SoC和A系列处理器SoC从事射频、毫米波和混合信号芯片的研发。2019年起到清华大学集成电路学院工作。邓伟副教授长期从事射频、毫米波和太赫兹芯片设计与系统集成，主持国家自然科学基金重点项目、国家重点研发计划课题等一系列国家科技项目。现任ISSCC、VLSI、CICC和ESSCIRC的技术委员会成员以及IEEE SSC-L期刊副主编，负责射频和无线方向。在JSSC、IEEE T-CAS I等期刊以及ISSCC、VLSI等国际会议发表论文120余篇，其中在JSSC和ISSCC发表论文20余篇，申请和授权发明专利20余项。获得过IEEE SSCS Predoctoral Achievement Award、Tejima Research Award和IEEE/ACM ASP-DAC Best Design Award等奖项。

研究领域

硅基射频、毫米波和太赫兹无线芯片全集成射频、毫米波和太赫兹微系统

近期论文

查看导师最新文章（温馨提示：请注意重名现象，建议点开原文通过作者单位确认）

Y. Sun, W. Deng, H. Jia, Y. He, Z. Wang and B. Chi, "A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique," in IEEE Journal of Solid-State Circuits (JSSC), doi: 10.1109/JSSC.2023.3266426. （Invited paper） Z. Lin, H. Jia, R. Ma, W. Deng, Z. Wang and B. Chi, "A Low-Phase-Noise VCO With Common-Mode Resonance Expansion and Intrinsic Differential 2nd-Harmonic Output Based on a Single Three-Coil Transformer," in IEEE Journal of Solid-State Circuits (JSSC), doi: 10.1109/JSSC.2023.3274178. Y. Yang, W. Deng, A. Yan, H. Jia, J. Gong, Z. Wang, and B. Chi, “A 10-to-300 MHz Fractional Output Divider with -80 dBc Worst-case Fractional Spurs using Auxiliary PLL based Background 0/1st/2nd-order DTC INL Calibration,” IEEE International Solid- State Circuits Conference (ISSCC), Feb. 2023, pp. 1-3, doi: 10.1109/ISSCC42615.2023.10067785. Q. Wu, W. Deng, H. Jia, H. Liu, S. Zhang, Z. Wang, B. Chi, “A 11.5-to-14.3 GHz 192.8-dBc/Hz FOM at 1MHz offset Dual-core Enhanced Class-F VCO with Common-mode Noise Self-cancellation and Isolation Technique,” IEEE International Solid- State Circuits Conference (ISSCC), pp. 7-9, Feb. 2023 H. Jia, P. Guan, W. Deng, Z. Wang and B. Chi, "A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS," in IEEE Journal of Solid-State Circuits (JSSC), vol. 58, no. 2, pp. 371-385, Feb. 2023, doi: 10.1109/JSSC.2022.3196181. W. Deng, Z. Chen, H. Jia, P. Guan, T. Ma, S. Sun, X. Huang, G. Chen, R. Ma, S. Dong, L. Duan, Z. Wang, and B. Chi, “A D-band Joint Radar-Communication CMOS Transceiver,” IEEE Journal of Solid-State Circuits (JSSC), vol. 58, no. 2, pp. 411-427, Feb. 2023, doi: 10.1109/JSSC.2022.3185160. W. Deng, Z. Chen, H. Jia, S. Sun. G. Chen. Z. Wang, and B. Chi, "A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW Signal Generation," IEEE Journal of Solid-State Circuits (JSSC), vol. 57, no. 4, pp. 1162-1174, April 2022 （Invited paper） H. Jia, R. Ma, W. Deng, Z. Wang and B. Chi, "A 53.6-to-60.2GHz Many-Core Fundamental Oscillator with Scalable Mesh Topology Achieving -136.0dBc/Hz Phase Noise at 10MHz Offset and 190.3dBc/Hz Peak FoM in 65nm CMOS," IEEE International Solid- State Circuits Conference (ISSCC), pp. 154-156 Feb. 2022 H. Jia, W. Deng, P. Guan, Z. Wang, and B. Chi,“A 60 GHz 186.5 dBc/Hz FOM Quad-Core Fundamental VCO using Circular-Triple-Coupled-Transformer with No Mode Ambiguity in 65nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021. W. Deng, Z. Song, R. Ma, J. Lin, J. Ye, S. Kong, S. Hu, H. Jia, and B. Chi, "An Energy-Efficient 10-Gb/s CMOS Millimeter-Wave Transceiver with Direct-Modulation Digital Transmitter and I/Q Phase-Coupled Frequency Synthesizer," IEEE Journal of Solid-State Circuits (JSSC), Vol. 55, No. 8, pp. 2027-2042, Aug. 2020 T. Ma, W. Deng, Z. Chen, J. Wu, W. Zheng, S. Wang, N. Qi, Y. Liu, B. Chi, "A CMOS 76-81 GHz 2TX/3RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator," IEEE Journal of Solid-State Circuits (JSSC), Vol. 55, No. 2, pp. 233-248, Feb. 2020 H. Liu, Z. Sun, H. Huang, W. Deng, T.Siriburanon, J. Pang, Y.Wang, R.Wu, T.Someya, A.Shirane, and K.Okada, "A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Sub-sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS," IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 12, pp. 3478-3492, Dec. 2019. （Invited paper） H.Liu, Z. Sun, H. Huang, W. Deng, T.Siriburanon, J. Pang, Y.Wang, R.Wu, T.Someya, A.Shirane, and K.Okada, "A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2019. （Invited to JSSC） H. Liu, D. Tang, Z. Sun, W. Deng, H. Ngo, and K. Okada, "A Sub-mW Fractional-N ADPLL with FOM of -246dB for IoT Applications," IEEE Journal of Solid-State Circuits (JSSC), Vol. 53, No. 12, Dec. 2018. Invited paper） H. Liu, Z.Sun, D. Tang, H. Huang, T.Kaneko, Z. Chen, W. Deng, R. Wu and K. Okada, "A DPLL-Centric Bluetooth Low-Energy Transceiver with a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65nm CMOS," IEEE Journal of Solid-State Circuits (JSSC), Vol. 53, No. 12, Dec. 2018. （Invited paper） H. Liu, D. Tang, Z. Sun, W. Deng, H. Ngo, K. Okada, and A. Matsuzawa, "A 0.98mW Fractional-N ADPLL Using 10b Isolated Constant-Slope DTC with FoM of -246dB for IoT Applications in 65nm CMOS," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2018. （Invited to JSSC） H. Liu, Z. Sun, D. Tang, H. Huang, T. Kaneko, W. Deng, R. Wu, K. Okada, and A. Matsuzawa, "An ADPLL-Centric Bluetooth Low-Energy Transceiver with 2.3mW Interference-Tolerant Hybrid-Loop Receiver and 2.9mW Single-Point Polar Transmitter in 65nm CMOS," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2018. （Invited to JSSC） A. Narayanan, M. Katsuragi, K. Kimura, S. Kondo, K.Tokgoz, K. Nakata, W. Deng, K. Okada, and A. Matsuzawa, "A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator with an FoM of -250dB," IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 7, pp. 1630-1640, Jul. 2016. （Invited paper） T. Siriburanon, S.Kondo, K. Kimura, T. Ueno, S. Kawashima, T. Kaneko, W. Deng, M. Miyahara, K. Okada, and A. Matsuzawa, "A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using Digital Sub-Sampling Architecture," IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No.6 , pp. 1385-1397, Jun. 2016. T. Siriburanon, S. Kondo, M. Katsuragi, H. Liu, K. Kimura, W. Deng, K. Okada, and A. Matsuzawa, "A Low-Power Low-Noise mm-Wave Sub-Sampling PLL using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE802.11ad," IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 5, pp. 1246-1260, May 2016. W. Deng, D. Yang, A. Narayanan, K. Nakata, T. Siriburanon, K. Okada, and A. Matsuzawa, "A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 252-253, Feb. 2015. T. Siriburanon, S. Kondo, K. Kimura, T. Ueno, S. Kawashima, T. Kaneko, W.Deng, M. Miyahara, K. Okada, A. Matsuzawa, "A 2.2-GHz -242dB-FoM 4.2-mW ADC-PLL Using Digital Sub-Sampling Architecture," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 440-441, Feb. 2015. W. Deng, D. Yang, T. Ueno, T. Siriburanon, S. Kondo, K. Okada, and A. Matsuzawa, "A Fully Synthesizable All-Digital PLL with Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique," IEEE Journal of Solid-State Circuits (JSSC), Vol. 50, No. 1, pp. 68-80, Jan. 2015. （Invited paper） W. Deng, S. Hara, A. Musa, K. Okada, and A. Matsuzawa, "A Compact and Low-power Fractionally Injection-Locked Quadrature Frequency Synthesizer using Self-Synchronized Gating Injection Technique for Software-Defined Radios," IEEE Journal of Solid-State Circuits (JSSC), Vol. 49, No. 9, pp. 1984-1994, Sep. 2014. W. Deng, D. Yang, T. Ueno, T. Siriburanon, S. Kondo, K. Okada, and A. Matsuzawa, "A 0.0066mm2 780µW Fully Synthesizable PLL with a Current Output DAC and an Interpolative-Phase Coupled Oscillator using Edge Injection Technique," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp.266-267, Feb. 2014. （Invited to JSSC） A. Musa, W. Deng, T. Siriburanon, M. Miyahara, K.Okada, and A. Matsuzawa, "A Compact, Low Power and Low Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration," IEEE Journal of Solid-State Circuits (JSSC), Vol. 49, No. 1, pp. 50-60, Jan. 2014. （Invited paper） W. Deng, T. Siriburanon, A. Musa, K. Okada, and A. Matsuzawa, "A Sub-harmonic Injection-locked Quadrature Frequency Synthesizer with Frequency Calibration Scheme for Millimeter-wave TDD Transceivers," IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 7, pp. 1710-1720, Jul. 2013. （Invited paper） W. Deng, A. Musa, T. Siriburanon, M. Miyahara, K. Okada, and A. Matsuzawa, "A 0.022mm2 970µW Dual-loop Injection-Locked PLL with -243dB FOM using Synthesizable All-Digital PVT Calibration Circuits," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 248-249, Feb. 2013. （Invited to JSSC） W. Deng, K. Okada, and A. Matsuzawa, " Class-C VCO with Amplitude Feedback Loop for Robust Start-up and Enhanced Oscillation Swing", IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 2, pp. 429-440, Feb. 2013.