王雪岩 - 北京航空航天大学 - 集成电路科学与工程学院

个人简介

王雪岩于2013年获得山东大学计算机科学与技术系学士学位，获“优秀毕业生”称号，并保送至清华大学计算机科学与技术系直博，于2018年获得工学博士学位，读博期间在美国马里兰大学帕克分校联合培养一年。2018年获批北航“卓越百人”博士后，2021年入职北航集成电路科学与工程学院教研系列助理教授。王雪岩在存内计算架构、软硬件协同设计和芯片安全等领域开展研究，提出的基于自旋存内计算架构的三角形计数图算法加速器，相比于传统冯诺依曼架构下FPGA/GPU等计算平台的加速方案速度和能效提升了一个数量级。近五年以第一作者/通讯作者在国际顶级会议和期刊，如IEEE TC、ACM/IEEE DAC、IEEE TCAD等，发表论文10余篇，参与撰写专著教材3部（《自旋电子科学与技术》、《集成电路设计自动化》、《Hardware Protection through Obfuscation》）。讲授本科生课程“计算机体系架构”、研究生课程“现代微纳电子学”（获评“北京市高校研究生课程思政示范课程”）、集成电路安全（领航华为实践课程）。她在IEEE SOCC 2021国际会议上作tutorial报告一次，在ACM/IEEE DAC、ACM/IEEE ASP-DAC、ACM GLSVLSI、IEEE ISCAS等国际会议上作口头报告累计5次。她是ACM/IEEE/CCF会员，受邀担任首届CCFDAC的出版主席（Publication Chair），以及IEEE DATE 2022、ACM/IEEE ASP-DAC 2022/2021/2020、IEEE SOCC 2022/2021/2020、ACM GLSVLSI 2020等学术会议的程序委员会（TPC）委员，ACM/IEEE ASP-DAC 2022/2020、CFTC 2019 分论坛主席，担任ACM TODAES、IEEE TCAD、IEEE TNANO、DATE等会议和期刊审稿人。教育经历 2013.9 -- 2018.7 清华大学计算机科学与技术博士研究生毕业工学博士学位 2015.2 -- 2016.2 University of Maryland, College Park 电子与计算机工程 2009.9 -- 2013.7 山东大学计算机科学与技术大学本科毕业工学学士学位工作经历 2021.10 -- 至今北京航空航天大学集成电路科学与工程学院助理教授 2018.11 -- 2021.10 北京航空航天大学集成电路科学与工程学院博士后

研究领域

存算一体架构、软硬件协同设计图计算/图神经网络隐私计算软硬件协同设计加速

近期论文

查看导师最新文章（温馨提示：请注意重名现象，建议点开原文通过作者单位确认）

Y. Wei, X. Wang, S. Bian, W. Zhao, Y. Jin, "THE-V: Verifiable Privacy-Preserving Neural Network via Trusted Homomorphic Execution", in IEEE/ACM International Conference on Computer-Aided Design (ICCAD).（通讯作者，集成电路设计自动化领域Top2会议） Y. Wei, X. Wang, S. Zhang, J. Yang, X. Jia, Z. Wang, G. Qu, W. Zhao, "IMGA: Efficient In-Memory Graph Convolution Network Aggregation with Data Flow Optimizations", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), doi: 10.1109/TCAD.2023.3288509. (通讯作者，CCF A类期刊) X. Chen, X. Wang, X. Jia, J. Yang, G. Qu, W. Zhao, "Accelerating Graph Connected Component Computation with Emerging Processing-In-Memory Architecture", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 41(12): 5333-5342, 2022. (通讯作者，CCF A类期刊) L. Yue, H. Zhang, X. Wang, H. Cai, Y. Zhang, S. Lv, R. Liu, W. Zhao, "Toward Energy-Efficient Sparse Matrix-Vector Multiplication with Near STT-MRAM Computing Architecture," 2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, 2023, pp. 222-227. (通讯作者，EDA领域著名会议) X. Wang, J. Yang, Y. Zhao, X. Jia, R. Yin, X. Chen, G. Qu, W. Zhao, "Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture," in IEEE Transactions on Computers (TC), 71(10): 2462-2472, 2022. (CCF A类期刊) X. Wang, J. Yang, Y. Zhao, Y. Qi, M. Liu, X. Cheng, X. Jia, X. Chen, G. Qu, and W. Zhao. Tcim: Triangle counting acceleration with processing-in-mram architecture. In 2020 57th ACM/IEEE Design Automation Conference (DAC), pages 1–6. IEEE, 2020. (CCF A 类，EDA领域最高会议，获得“最佳论文候选”) X. Wang, Q. Zhou, Y. Cai, and G. Qu. Toward a formal and quantitative evaluation framework for circuit obfuscation methods. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 38(10):1844–1857, 2019. (CCF A类期刊) X. Wang, J. Yang, Y. Zhao, X. Jia, G. Qu, and W. Zhao. Hardware security in spin-based computing-in-memory: Analysis, exploits, and mitigation techniques. ACM Journal on Emerging Technologies in Computing Systems (JETC), 16(4):1–18, 2020. X. Wang, Q. Zhou, Y. Cai, and G. Qu. Parallelizing sat-based de-camouflaging attacks by circuit partitioning and conflict avoiding. Integration, 67:108–120, 2019. X. Wang, Q. Zhou, Y. Cai, and G. Qu. A conflict-free approach for parallelizing sat-based de-camouflaging attacks. In 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pages 259–264. IEEE, 2018. (接收率：32%) X. Wang, Q. Zhou, Y. Cai, and G. Qu. Spear and shield: Evolution of integrated circuit camouflaging. Journal of Computer Science and Technology (JCST), 33(1):42–57, 2018. (CCF B类期刊) X. Wang, M. Gao, Q. Zhou, Y. Cai, and G. Qu. Gate camouflaging-based obfuscation. In Hardware Protection through Obfuscation, pages 89–102. Springer, 2017. (专著) X. Wang, Q. Zhou, Y. Cai, and G. Qu. An empirical study on gate camouflaging methods against circuit partition attack. In Proceedings of the on Great Lakes Symposium on VLSI (GLSVLSI), pages 345–350, 2017. (接收率：24%) X. Wang, Y. Cai, and Q. Zhou. Cell spreading optimization for force-directed global placers. In 2017 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1–4. IEEE, 2017. X. Wang, X. Jia, Q. Zhou, Y. Cai, J. Yang, M. Gao, and G. Qu. Secure and low-overhead circuit obfuscation technique with multiplexers. In 2016 International Great Lakes Symposium on VLSI (GLSVLSI), pages 133–136. IEEE, 2016. (接收率：25%) X. Wang,, Q. Zhou, Y. Cai, and G. Qu. Is the secure ic camouflaging really secure? In 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pages 1710–1713. IEEE, 2016. X. Jia, H. Gu, Y. Liu, J. Yang, X. Wang, W. Pan, Y. Zhang, S. D. Cotofana, and W. Zhao, An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method, in IEEE Transactions on Neural Networks and Learning Systems (TNNLS), doi: 10.1109/TNNLS.2023.3265533. X. Jia, J. Yang, R. Liu, X. Wang, S. D. Cotofana, and W. Zhao. Efficient computation reduction in bayesian neural networks through feature decomposition and memorization. IEEE transactions on neural networks and learning systems (TNNLS), 32(4):1703–1712, 2020. Y. Pan, X. Jia, Z. Cheng, P. Ouyang, X. Wang, J. Yang, and W. Zhao. An stt-mram based reconfigurable computing-in-memory architecture for general purpose computing. CCF Transactions on High Performance Computing, 2(3):272–281, 2020. Y. Zhao, J. Yang, X. Jia, X. Wang, Z. Wang, W. Kang, Y. Zhang, and W. Zhao. Exploiting near-memory processing architectures for bayesian neural networks acceleration. In 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pages 203–206. IEEE, 2019. J. Yang, X. Wang, Q. Zhou, Z. Wang, H. Li, Y. Chen, and W. Zhao. Exploiting spin-orbit torque devices as reconfigurable logic for circuit obfuscation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 38(1):57–69, 2018. S. Jiang, N. Xu, X. Wang, and Q. Zhou. An efficient technique to reverse engineer minterm protection based camouflaged circuit. Journal of Computer Science and Technology (JCST), 33(5):998–1006, 2018. Q. Zhou, X. Wang, Z. Qi, Z. Chen, Q. Zhou, and Y. Cai. An accurate detailed routing routability prediction model in placement. In 2015 6th Asia Symposium on Quality Electronic Design (ASQED), pages 119–122. IEEE, 2015.