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Yuanqing Cheng, Lei Zhang, Yinhe Han, Jun Liu and Xiaowei Li, "Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC", in Proceedings of IEEE Asian Test Symposium (ATS), New Delhi, India, Nov. 2011, pp. 181-186.
Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vevet and Marc Belleville, "A novel method to mitigate TSV electromigration for 3D ICs", in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Natal, Brazil, Jul. 2013, pp. 121-126.
Yuanqing Cheng, Lei Zhang, Yinhe Han, and Xiaowei Li, "TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design", Journal of Computer Science and Technology (JCST), vol. 28, no. 1, pp. 119-128, 2013.
Yuanqing Cheng, Lei Zhang, Yinhe Han, and Xiaowei Li, "Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 21, no. 2, pp. 239-249, 2013.
Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, and Arnaud Virazel, "Power Supply Noise-Aware Workload Assignments for Homogenous 3D MPSoCs with Thermal Consideration", in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Singapore, Jan. 2014, pp.544-549.
Xiaolong Zhang, Yuanqing Cheng*, Weisheng Zhao, Youguang Zhang and Aida Todri-Sanial, "Exploring Potentials of Perpendicular Magnetic Anisotropy STT-MRAM for Cache Design", in Proceedings of IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Guilin, China, Oct. 2014, pp. 893-895.
Jun Zhou, Huawei Li, Yuntan Fang, Tiancheng Wang, Yuanqing Cheng and Xiaowei Li, "HARS: A High-Performance Reliable Routing Scheme for 3D NoCs", in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, FL, USA, Jul. 2014, pp. 392-397.
Lun Yang, Yuanqing Cheng*, Ying Wang, Hao Yu, Weisheng Zhao and Aida Todri-Sanial, "A body-biasing of readout circuit for STT-RAM with improved thermal reliability", in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 2015, pp. 1530-1533.
Xiaolong Zhang, Yuanqing Cheng*, Ying Wang, Weisheng Zhao and Aida Todri-Sanial, "Write back energy optimization for STT-RAM based cache using data pattern characterization", IEEE/ACM Design Automation Conference (DAC) WIP session, San Francisco, CA, USA, Jun. 2015.
Bi Wu, Yuanqing Cheng*, Ying Wang, Aida Todri-Sanial, Guangyu Sun, Lionel Torres and Weisheng Zhao, "An architecture-level cache simulation framework supporting advanced PMA STT-MRAM", in Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Boston, MA, USA, Jul. 2015, pp. 7-12.
Liuyang Zhang, Wang Kang, Youguang Zhang, Yuanqing Cheng, Lang Zeng, Jacques-Olivier Klein and Weisheng Zhao, "Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM", in Proceedings of IEEE Computer Society Annual Symposium on VLSI, Montpellier, France, Jul. 2015, pp. 461-466.
Ying Wang, Lili Song, Yinhe Han, Yuanqing Cheng, Huawei Li and Xiaowei Li, "A case of precision-tunable STT-RAM memory design for approximate neural network", in Proceedings of International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 2015, pp. 1534-1537.
Yuanqing Cheng*, Aida Todri-Sanial, Jianlei Yang and Weisheng Zhao, "Alleviating Through Silicon Via Electromigration for Three-dimensional Integrated Circuits Taking Advantage of Self-healing Effect", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 24, no. 11, pp. 3310-3322, 2016.
Ping Chi, Shuangchen Li, Yuanqing Cheng, Yv Lu, S. H. Kang and Yuan Xie, "Architecture Design with STT-RAM: Opportunities and Challenges", in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Macao, China, Jan. 2016, pp.109-114.
Aida Todri-Sanial and Yuanqing Cheng, "A Study of 3-D Power Delivery Networks With Multiple Clock Domains", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 24, no. 11, pp. 3218-3231, 2016.
Linuo Xue, Yuanqing Cheng*, Jianlei Yang, Peiyuan Wang and Yuan Xie, "ODESY: A novel 3T-3MTJ cell design with Optimized area DEnsity, Scalability and latency", in Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD), Austin, TX, USA, Nov. 2016, pp. 1-8.
"Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM", IEEE Transactions on Reliability, vol. 65, no. 4, pp. 1755-1768, 2016.
Bi Wu, Yuanqing Cheng*, Jianlei Yang, Aida Todri-Sanial and Weisheng Zhao, Liang Wu, Xiaoxiao Wang, Xiaoying Zhao, Yuanqing Cheng, Donglin Su, Aixin Chen, Qihang Shi and Mark Tehranipoor, "AES design improvement towards information safety", in Proceedings of International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 2016, pp. 1706-1709.
Liuyang Zhang, Aida Todri-Sanial, Wang Kang, Youguang Zhang, Lionel Torres, Yuanqing Cheng* and Weisheng Zhao, "Quantitative evaluation of reliability and performance for STT-MRAM", in Proceedings of International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 2016, pp. 1150-1153.
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