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[1] W. Dai, Y. Li, Z. Rong, B. Peng, L. Zhang*, R. Wang*, R. Huang, “Statistical compact modeling with artificial neural networks,” to appear IEEE Trans. Computer-aided Design of Integrated Circuits and Systems, 2023
[2] F. Zhang, H. Li, K. Wang, W. Dai, Y. Jiao, F. Ding, Y. Ren, Y. Wu, W. Bu, Q. Huang, L. Zhang*, R. Huang, “A surface potential based full region current model for Si DS-TFET,” to appear IEEE Trans. Electron Devices, 2023
[3] N. Feng, H. Li, B. Peng, F. Zhang, P. Cai, L. Zhang*, R. Wang*, R. Huang, “Metal-ferroelectric- semiconductor tunnel junction: essential physics and design explorations,” IEEE Trans. Electron Devices, vol. 70, no. 6, pp. 3382-3389, June 2023
[4] Q. Hu, C. Gu, Q. Li, S. Zhu, S. Liu, Y. Li, L. Zhang, R. Huang, Y. Wu, “True nonvolatile high-speed DRAM cells using tailored ultrathin IGZO,” Advanced Materials, vol. 35, no. 20, pp. 2210554, May 2023
[5] C. J. Estrada, Z. Ma, L. Zhang, M. Chan, “Threshold voltage model for 2-D FETs with undoped body and gated source,” IEEE Trans. Electron Devices, vol. 70, no. 5, pp. 2575-2580, May 2023
[6] N. Feng, H. Li, L. Zhang*, N. Ji, F. Zhang, X. Zhu, Z. Shang, P. Cai, M. Li, R. Wang, R. Huang, “A physics-based dynamic compact model of ferroelectric tunnel junctions,” IEEE Electron Device Letters, vol. 44, no. 2, pp. 261-264, Feb. 2023
[7] B. Peng, Y. Jiao, H. Zhong, Z. Rong, Z. Wang, Y. Xiao, W. Wong, L. Zhang*, R. Wang*, R. Huang, “Compact modeling of quantum confinements in nanoscale gate-all-around MOSFETs,” accepted by Fundamental Research, 2022
[8] L. Zhang*, M. Chan, “Editorial: Hardware Implementation of Spike-based Neuromorphic Computing and its Design Methodologies,” Frontiers in NeuroScience, doi: 10.3389/fnins.2022.1113983
[9] D. Wang, L. Zhou, Y. Xue, P. Ren, L. Zhang, X. Li, X. Liu, J. Wang, B. Wu, Z. Ji* , R. Wang*, K. Cao and R. Huang, “Defect-Based Empirical Model for On-State Degradation in Sub-20-nm DRAM Periphery pFETs Under Arbitrary Condition,” IEEE Trans. Electron Devices, vol. 69, no. 12, pp. 6669-6675, Dec. 2022
[10] F. Ding, Y. Jiao, B. Peng, H. Li, W. Liu, L. Zhang*, R. Wang, R. Huang, “Modeling the gradual RESET of phase change memory with confined geometry,” IEEE Trans. Electron Devices, vol. 69, no. 12, pp. 6662-6668, Dec. 2022
[11] Y. Li, X. Huang, C. Liao, R. Wang, S. Zhang, L. Zhang*, R. Huang, “A dynamic current hysteresis model for IGZO-TFT,” Solid-State Electronics, vol. 197, pp. 108459, Sept. 2022
[12] Z. Wang, Y. Lv, L. Zhang, L. Liao, C. Jiang, “Strain release enabled bandgap scaling in Ge nanowire and tunnel FET application,” IEEE Trans. Electron Devices, vol. 69, no. 8, pp. 4725-4729, Aug. 2022
[13] Z. Ma, C. Estrada, K. Gong, L. Zhang*, M. Chan, “On-chip integrated high gain complementary MoS2 inverter circuit with exceptional high hole current p-channel field-effect transistors,” Adv. Elec. Mater., doi.org/10.1002/aelm.202200480, July 2022
[14] Y. Jiao, X. Huang, Z. Rong, Z. Ji, R. Wang, L. Zhang*, “Modeling multigate negative capacitance transistors with self-heating effects,” IEEE Trans. Electron Devices, vol. 69, no. 6, pp. 3029-3036, June. 2022
[15] N. Feng, H. Li, C. Su, L. Zhang*, Q. Huang, R. Wang, R. Huang, “A dynamic compact model for ferroelectric capacitance,” IEEE Electron Device Letters, vol. 43, no. 2, pp. 390-393, Mar. 2022
[16] F. Ding, B. Peng, X. Li, L. Zhang*, R. Wang, Z. Song, R. Huang, “A review of compact modeling for phase change memory,” J. of Semi., vol. 43, no. 2, pp. 023101, Feb. 2022
[17] F. Ding, D. Dong, Y. Chen, X. Lin, L. Zhang*, “Robust simulations of nanoscale phase change memory: dynamics and retention,” Nanomaterials, vol. 11, no. 11, pp. 2945, Nov. 2021
[18] X. Chen, F. Ding, X. Huang, X. Lin, R. Wang, M. Chan, L. Zhang*, R. Huang, “A robust and efficient compact model for phase change memory circuit simulations,” IEEE Trans. Electron Devices, vol. 68, no. 9, pp. 4404-4410, Sept. 2021
[19] X. Huang, X. Chen, L. Li, H. Zhong, Y. Jiao, X. Lin, Q. Huang, Lining Zhang*, Ru Huang, “A dynamic current model for MFIS negative capacitance transistors,” IEEE Trans. Electron Devices, vol. 68, no. 7, pp. 3665-3671, July 2021
[20] Z. Huang, S. Xiong, N. Dong, Lining Zhang, X. Lin, “A Study of the gate-stack small-signal model and determination of interface traps in GaN-based MIS-HEMT,” IEEE Trans. Electron Devices, vol. 67, no. 4, pp. 1507-1512, Apr. 2021
[21] Z. Ma, Lining Zhang*, C. Zhou, M. Chan, “High current Nb-doped P-channel MoS2 field-effect transistor using Pt contact,” IEEE Electron Device Letters, vol. 42, no. 3, pp. 343-346, Mar. 2021
[22] X. Chen, F. Hu, X. Huang, W. Cai, M. Liu, C. Lam, X. Lin, Lining Zhang*, M.Chan, “A SPICE model of phase change memory for neuromorphic circuits,” IEEE Access, vol. 8, pp.95278-95287, May 2020
[23] Z. Rong, W. Cai, Y. Zhang, P. Wu, X. Li, Lining Zhang*, “On the enhanced Miller capacitance of source- gated thin film transistors,” IEEE Electron Device Letters, vol.41, no.5, pp. 741-744, May 2020
[24] Z. Ahmed, Q. Shi, Z. Ma, Lining Zhang*, H. Guo, M. Chan, “Analytical Monolayer MoS2 MOSFET Modeling Verified by First Principle Simulations,” IEEE Electron Device Letters, vol. 41, no. 1, pp. 171-174, Jan. 2020
[25] H. Hu, D. Liu, X. Chen, D. Dong, X. Cui, M. Liu, X. Lin, Lining Zhang*, M. Chan, “A compact phase change memory model with dynamic state variables,” IEEE Trans. Electron Devices, vol. 67, no. 1, pp. 133-139, Jan. 2020
[26] Lining Zhang*, L. Wang, W. Wu, M. Chan, “Modeling Current–Voltage Characteristics of Bilayer Organic Light-Emitting Diodes,” IEEE Trans. Electron Devices, vol. 66, no. 1, pp. 139-145, Jan. 2019
[27] Lining Zhang*, C. Ma, Y. Xiao, H. Zhang, X. Lin, M. Chan, “A dynamic time evolution method for concurrent device-circuit aging simulations,” IEEE Trans. Electron Devices, vol. 66, no. 1, pp. 184-190, Jan. 2019
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