梁宇华 - 西安电子科技大学

个人简介

梁宇华男，1986年生，山西岚县人，九三学社社员。长期从事模拟前端电路、混合信号集成电路设计及基于新型器件的模拟电路设计研究。已在国际知名期刊IEEE TED、IEEE TCAS-I、IEEE TCAS-II、IEEE SENSORS JOURNAL、MICROELECTRONIC JOURNAL等SCI期刊上发表相关期刊论文二十余篇；担任IEEE TED、IEEE EDL、IEEE TCAS-I、MICROELECTRONIC JOURNAL等SCI期刊审稿人；先后主持了国家自然科学基金面上项目、国家自然科学基金青年项目、陕西省重点研发计划项目、陕西省教育厅重点项目、国家重点研发计划课题项目、中国博士后基金面上项目等项目。 2020.05-至今西安电子科技大学微电子学院副教授/硕士生导师 2017.07-2018.07 美国宾夕法尼亚州立大学计算机科学与工程系研究助理教授 2017.07-2020.04 西安电子科技大学微电子学院讲师/硕士生导师 2016.03-2017.07 西安电子科技大学微电子学院师资博士后

研究领域

1、数据转换器及模拟前端电路设计（1）高速逐次逼近型模数转换器；（2）混合信号域（电压域-时间域）高速模数转换器及低功耗模数转换器；（3）模拟前端电路 2、基于负电容晶体管（NCFET）的器件、电路及系统研究（1）器件SPICE建模；（2）基于NCFET的模拟电路研究；（3）基于NCFET的低功耗模数转换器研究

近期论文

查看导师新发文章（温馨提示：请注意重名现象，建议点开原文通过作者单位确认）

Yuhua Liang, Ruixue Ding, Zhangming Zhu*. A 9.1ENOB 200MS/s Asynchronous SAR ADC With Hybrid Single-Ended/Differential DAC in 55-nm CMOS for Image Sensing Signals [J]. IEEE Sensors Journal, July. 2018，vol.18, no.17, pp: 7130-7140. Zhangming Zhu*, Yuhua Liang. A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-μm CMOS for Medical Implant Devices [J]. IEEE Transactions on Circuits and Systems I, Sep. 2015，vol.62, no.9, pp: 2167-2176. Yi Xie, Yuhua Liang, Maliang Liu, Shubin Liu, Zhangming Zhu*. A 10-Bit 5 MS/s VCO-SAR ADC in 0.18-μm CMOS [J]. IEEE Transactions on Circuits and Systems II, Jan. 2019, vol.66, no.1, pp: 26-30. Yuhua Liang, Zhangming Zhu*, et al. Utilization of Negative Capacitance FETs to Boost Analog Circuit Performances," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, accepted. Yuhua Liang, Xueqing Li, et al. Influence of Body Effect on Sample-and-Hold Circuit Design Using Negative Capacitance FET [J]. IEEE Transactions on Electron Device, Aug. 2018，vol.65, no.9, pp: 3909-3914. Yuhua Liang, Xueqing Li, et al. Analysis of DIBL Effect and Negative Resistance Performance for NCFET Based on a Compact SPICE Model [J]. IEEE Transactions on Electron Device, Nov. 2018, vol.65, no.12, pp: 5525-5529. Yuhua Liang, Zhangming Zhu*, Ruixue Ding. A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65nm CMOS [J]. Microelectronics Journal, Oct. 2015，vol.46, no.10, pp: 988-995. Yuhua Liang, Zhangming Zhu*. A 10bit 20 kS/s 17.7 nW 9.1ENOB reference-insensitive SAR ADC in 0.18 um CMOS [J]. Microelectronics Journal, March. 2018，vol.73, pp: 24-29. Yuhua Liang, Zhangming Zhu*, Ruixue Ding. SAR ADC architecture with 98.8 % reduction in switching energy over conventional scheme [J]. Analog Integrated Circuits and Signal Processing, Jul. 2015, vol. 84, no. 1, pp: 89-96. Yuhua Liang, Zhangming Zhu*. Journal of Circuits Systems and Computers, Aug. 2015, vol. 24, no. 7. Yuhua Liang, Zhangming Zhu*. An energy-efficient switching-scheme for low-power SAR ADC design [J]. Journal of Circuits Systems and Computers, Jan. 2018, vol. 27, no. 1. Yuhua Liang, Zhangming Zhu*. Analysis and modeling of a SAR-VCO hybrid ADC architecture [J]. Journal of Circuits Systems and Computers, March. 2018, vol. 27, no. 3. Yuhua Liang, Zhangming Zhu*, Ruixue Ding. Microelectronics Journal, Oct. 2015，vol.46, no.10, pp: 963-969. Xueqing li, Sumitha George, Yuhua Liang, et al. Lowering Area Overheads for FeFET-Based Energy-Efficient Nonvolatile Flip-Flops [J]. IEEE Transactions on Electron Device, June. 2018, vol.65, no.6, pp: 2670-2674. Yuhua Liang, Zhangming Zhu*. A 0.6V 31nW 25ppm/C MOSFET-only subthreshold voltage reference [J]. Microelectronics Journal, June. 2017，vol.66, pp: 25-30. Yuhua Liang, Zhangming Zhu*, Ruixue Ding. Strategy for SAR ADC with 87.5% area saving and 99.4% switching energy reduction over conventional approach [J]. IEICE Electronics Express, Apr. 2015, vol. 12, no. 8, pp: 1-6. Yuhua Liang, Zhangming Zhu*. A 42ppm/C 0.7V 47nW Low-complexity All-MOSFET sub-threshold voltage reference [J]. Journal of Circuits Systems and Computers, Nov. 2018, vol. 27, no. 7.