Textured Poling of the Ferroelectric Dielectric Layer for Improved Organic Field‐Effect Transistors,Advanced Materials Interfaces

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Textured Poling of the Ferroelectric Dielectric Layer for Improved Organic Field‐Effect Transistors
Advanced Materials Interfaces ( IF 4.3 ) Pub Date : 2019-01-09 , DOI: 10.1002/admi.201801787
Amrit Laudari ₁ , Alec Pickett ₁ , Fatemeh Shahedipour-Sandvik ₂ , Kasey Hogan ₂ , John E. Anthony ₃ , Xiaoqing He ₄ , Suchismita Guha ₁

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Polymer ferroelectrics are playing an increasingly active role in flexible memory application and wearable electronics. The relaxor ferroelectric dielectric, poly(vinylidene fluoride trifluorethylene (PVDF‐TrFE), although vastly used in organic field‐effect transistors (FETs), has issues with gate leakage current especially when the film thickness is below 500 nm. This work demonstrates a novel method of selective poling the dielectric layer. By using solution‐processed 6,13‐bis(triisopropylsilylethynyl)pentacene (TIPS‐pentacene) as the organic semiconductor, it is shown that textured poling of the PVDF‐TrFE layer dramatically improves FET properties compared to unpoled or uniformly poled ferroelectric films. The texturing is achieved by first vertically poling the PVDF‐TrFE film and then laterally poling the dielectric layer close to the gate electrode. TIPS‐pentacene FETs show on/off ratios of 10⁵ and hole mobilities of 1 cm² Vs⁻¹ under ambient conditions with operating voltages well below −5 V. The electric field distribution in the dielectric layer is simulated by using finite difference time domain methods.

中文翻译：

铁电介质层的纹理化极化，用于改进有机场效应晶体管

聚合物铁电材料在柔性存储器应用和可穿戴电子产品中发挥着越来越积极的作用。弛豫铁电介质聚偏二氟乙烯三氟乙烯（PVDF-TrFE）尽管已广泛用于有机场效应晶体管（FET）中，但栅极漏电流存在问题，尤其是在膜厚度小于500 nm时。通过使用溶液处理的6,13-双（三异丙基甲硅烷基乙炔基）并五苯（TIPS-并五苯）作为有机半导体，可以显示出PVDF-TrFE层的织构化极化可以显着改善FET性能未极化或均匀极化的铁电薄膜。通过首先垂直极化PVDF-TrFE膜，然后横向极化靠近栅电极的电介质层来实现纹理化。TIPS并五苯FET的开/关比为10在环境条件下，其工作电压远低于-5 V时，空穴迁移率为⁵，空穴迁移率为1 cm ² Vs ^-1。使用有限差分时域方法模拟介电层中的电场分布。

更新日期：2019-01-09

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