Excellent Device Performance of Sub‐5‐nm Monolayer Tellurene Transistors,Advanced Electronic Materials

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Excellent Device Performance of Sub‐5‐nm Monolayer Tellurene Transistors
Advanced Electronic Materials ( IF 5.3 ) Pub Date : 2019-05-28 , DOI: 10.1002/aelm.201900226
Jiahuan Yan ₁ , Hua Pang ₁ , Lin Xu ₂ , Jie Yang ₁ , Ruge Quhe ₃ , Xiuying Zhang ₁ , Yuanyuan Pan ₁ , Bowen Shi ₁ , Shiqi Liu ₁ , Lianqiang Xu ₄ , Jinbo Yang _{1,

5,

6} , Feng Pan ₇ , Zhiyong Zhang ₂ , Jing Lu _{1,

5,

6}

Affiliation

The merging 2D semiconductor tellurene (2D Group‐VI tellurium) is a possible channel candidate for post‐silicon field‐effect transistor (FETs) due to its high carrier mobility, high drive current, and excellent air stability. The performance limits of sub‐5‐nm ML tellurene metal‐oxide‐semiconductor FETs (MOSFETs) are explored by employing exact ab initio quantum transport simulations. An optimized p‐type ML tellurene MOSFET meets both the high performance (along both the armchair and the zigzag directions) and the low power (along the armchair direction) requirements of the International Technology Roadmap for Semiconductors (ITRS) at a gate length of 4 nm with a negative capacity dielectric. Hence, choosing ML tellurene as the channel material provides a novel route to continue the Moore's law to 4 nm.

中文翻译：

5nm以下单层碲铝晶体管的出色器件性能

由于具有高载流子迁移率，高驱动电流和出色的空气稳定性，合并的2D半导体碲（2D Group-VI碲）可能成为后硅场效应晶体管（FET）的候选通道。通过采用精确的从头算起的量子传输模拟，探索了亚5纳米以下ML碲烯金属氧化物半导体FET（MOSFET）的性能极限。经过优化的p型ML碲硅MOSFET在栅极长度为4时满足了国际半导体技术路线图（ITRS）的高性能（沿扶手椅和锯齿形方向）和低功耗（沿扶手椅子方向）的要求。负电容电介质。因此，选择ML碲烯作为通道材料提供了一条将摩尔定律延续到4 nm的新颖途径。

更新日期：2019-05-28

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