Neural decoders for quantum error correction rely on neural networks to classify syndromes extracted from error correction codes and find appropriate recovery operators to protect logical information against errors. Its ability to adapt to hardware noise and long-term drifts make neural decoders promising candidates for inclusion in a fault-tolerant quantum architecture. However, given their limited scalability, it is prudent that small-scale (local) neural decoders are treated as first stages of multi-stage decoding schemes for fault-tolerant quantum computers with millions of qubits. In this case, minimizing the decoding time to match the stabilization measurements frequency and a tight co-integration with the QPUs is highly desired. Cryogenic realizations of neural decoders can not only improve the performance of higher stage decoders, but they can minimize communication delays, and alleviate wiring bottlenecks. In this work, we design and analyze a neural decoder based on an in-memory computation (IMC) architecture, where crossbar arrays of resistive memory devices are employed to both store the synaptic weights of the neural decoder and perform analog matrix–vector multiplications. In simulations supported by experimental measurements, we investigate the impact of TiOx-based memristive devices’ non-idealities on decoding fidelity. We develop hardware-aware re-training methods to mitigate the fidelity loss, restoring the ideal decoder’s pseudo-threshold for the distance-3 surface code. This work provides a pathway to scalable, fast, and low-power cryogenic IMC hardware for integrated fault-tolerant quantum error correction.

中文翻译：

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用于低温容错量子纠错的忆阻神经解码器


用于量子纠错的神经解码器依靠神经网络对从纠错码中提取的综合征进行分类，并找到合适的恢复运算符来保护逻辑信息免受错误的影响。它能够适应硬件噪声和长期漂移，使神经解码器成为容错量子架构的候选者。然而，鉴于其可扩展性有限，谨慎的做法是将小规模（本地）神经解码器视为具有数百万个量子比特的容错量子计算机的多级解码方案的第一阶段。在这种情况下，非常需要最小化解码时间以匹配稳定测量频率并与 QPU 紧密共集成。神经解码器的低温实现不仅可以提高更高级解码器的性能，还可以最大限度地减少通信延迟，并缓解布线瓶颈。在这项工作中，我们设计并分析了一个基于内存计算 （IMC） 架构的神经解码器，其中电阻式存储设备的交叉条阵列用于存储神经解码器的突触权重并执行模拟矩阵-向量乘法。在实验测量支持的仿真中，我们研究了基于 TiOx 的忆阻器件的非理想性对解码保真度的影响。我们开发了硬件感知的再训练方法来减轻保真度损失，恢复距离 3 表面代码的理想解码器伪阈值。这项工作为可扩展、快速和低功耗的低温 IMC 硬件提供了一条途径，用于集成容错量子纠错。