The development of quantum computers will require the careful management of the noise effects associated with qubit performance. However, the decoders responsible for diagnosing noise-induced computational errors must use resources efficiently to enable scaling to large qubit counts and cryogenic operation. They must also operate at speed, to avoid an exponential slowdown in the logical clock rate of the quantum computer. To overcome these challenges, we introduce the Collision Clustering decoder and demonstrate its implementation on field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) hardware. We simulate logical memory experiments using the leading quantum error correction scheme (the surface code) and demonstrate megahertz decoding speed—matching the requirements of fast-operating modalities such as superconducting qubits—up to an 881 qubit surface code with the FPGA and 1,057 qubit surface code with the ASIC. The ASIC design occupies 0.06 mm² and consumes only 8 mW of power.

量子计算机的开发将需要仔细管理与量子比特性能相关的噪声效应。但是，负责诊断噪声引起的计算错误的解码器必须有效地使用资源，以实现扩展到大量子比特数和低温操作。它们还必须高速运行，以避免量子计算机的逻辑时钟速率呈指数级减慢。为了克服这些挑战，我们推出了 Collision Clustering 解码器，并演示了它在现场可编程门阵列 （FPGA） 和专用集成电路 （ASIC） 硬件上的实现。我们使用领先的量子纠错方案（表面代码）来模拟逻辑内存实验，并展示了兆赫兹解码速度（符合超导量子比特等快速操作模式的要求），FPGA 高达 881 量子比特表面代码，ASIC 高达 1,057 量子比特表面代码。ASIC 设计占用 0.06 mm²，功耗仅为 8 mW。