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P-type NiOX dielectric-based CMOS inverter logic gate using enhancement-mode GaN nMOS and diamond pMOS transistors
Applied Physics Letters ( IF 3.5 ) Pub Date : 2024-12-16 , DOI: 10.1063/5.0231002
Mahalaxmi Patil, Subrat K. Pradhan, Vivek K. Shukla, Padmnabh Rai, Jayanti Paul, Aaqib H. Sheikh, Bazila Parvez, Swaroop Ganguly, Kasturi Saha, Dipankar Saha

We have demonstrated a complementary metal-oxide-semiconductor inverter logic gate by heterogeneous integration of an enhancement-mode n-channel transistor on GaN and a p-channel transistor on diamond. A thermally grown p-type NiOx is used as the dielectric, and Ni/Au is the gate metal for both transistors. NiOx oxide on top of a partially recessed-gate AlGaN/GaN heterostructure depletes the two-dimensional electron gas by pulling the Fermi level closer to the valence band and making it normally OFF. The combination of Ni/NiOx gate metal work function and the dielectric helps to deplete the two-dimensional hole gas channel of a hydrogen-terminated p-channel diamond, making it an enhancement mode. The GaN n-MOS and diamond p-MOS transistors show output and transfer characteristics with threshold voltages of +0.6 and −1.2 V, respectively. nMOS and pMOS transistors show ION/IOFF current ratios of >105 and >103, respectively, with a subthreshold leakage of <10 μA/mm. The gate current is negligible for both devices. The saturation drain current of the respective transistors is measured to be ∼170 and ∼20 mA/mm at a gate-to-source overdrive voltage of 3 V. The inverter input–output characteristics and transient response are measured for various rail-to-rail voltages and frequencies. The inverter threshold voltage is measured to be 1.1 V for a nominal operating voltage of 3 V.

中文翻译:


使用增强型 GaN nMOS 和金刚石 pMOS 晶体管的 P 型 NiOX 电介质基 CMOS 反相逻辑门



我们已经通过在 GaN 上异构集成增强型 n 沟道晶体管和金刚石上的 p 沟道晶体管,展示了互补金属氧化物半导体反相逻辑门。热生长的 p 型 NiOx 用作电介质,Ni/Au 是两个晶体管的栅极金属。部分凹陷栅极 AlGaN/GaN 异质结构顶部的 NiOx 氧化物通过将费米能级拉近价带并使其正常关闭来耗尽二维电子气。Ni/NiOx 栅极金属功函数和电介质的结合有助于耗尽氢封端 p 通道金刚石的二维空穴气体通道,使其成为一种增强模式。GaN n-MOS 和金刚石 p-MOS 晶体管在阈值电压分别为 +0.6 V 和 −1.2 V 时表现出输出和传输特性。nMOS 和 pMOS 晶体管的 ION/IOFF 电流比分别为 >105 和 >103,亚阈值泄漏为 <10 μA/mm。两种器件的栅极电流都可以忽略不计。在 3 V 的栅源过驱动电压下,测得各个晶体管的饱和漏极电流为 ∼170 和 ∼20 mA/mm。逆变器的输入-输出特性和瞬态响应是针对各种轨到轨电压和频率测量的。当标称工作电压为 3 V 时,逆变器阈值电压的测量值为 1.1 V。
更新日期:2024-12-16
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