Atomically thin two-dimensional (2D) semiconductors—particularly transition metal dichalcogenides—are potential channel materials for post-silicon complementary metal–oxide–semiconductor (CMOS) field-effect transistors. However, their application in CMOS technology will require implementation in three-dimensional (3D) transistors. Here we report a framework for designing scaled 3D transistors using 2D semiconductors. Our approach is based on non-equilibrium Green’s function quantum transport simulations that incorporate the effects of non-ideal Schottky contacts and inclusive capacitance calculations, with material inputs derived from density functional theory simulations. A comparative performance analysis of different 3D transistors (2D and silicon based) and channel thicknesses is carried out for both low-standby-power and high-performance applications. This suggests that trilayer tungsten disulfide is the most promising material, offering an improvement in energy–delay product of over 55% compared with silicon counterparts, potentially extending CMOS scaling down to a few nanometres. We also show that 2D semiconductors could be uniquely engineered to create 2D nanoplate field-effect transistors that offer nearly tenfold improvement in integration density and drive current over both 2D- and silicon-based 3D field-effect transistors with similar footprints.

原子薄的二维 （2D） 半导体（尤其是过渡金属二硫化物）是硅后互补金属氧化物半导体 （CMOS） 场效应晶体管的潜在通道材料。然而，它们在 CMOS 技术中的应用需要在三维 （3D） 晶体管中实现。在这里，我们报告了一个使用 2D 半导体设计缩放 3D 晶体管的框架。我们的方法基于非平衡格林函数量子输运模拟，该模拟结合了非理想肖特基接触和包容性电容计算的影响，以及从密度泛函理论模拟中获得的材料输入。针对低待机功耗和高性能应用，对不同的 3D 晶体管（2D 和硅基）和通道厚度进行了比较性能分析。这表明三层二硫化钨是最有前途的材料，与硅相比，能量延迟积提高了 55% 以上，有可能将 CMOS 缩小到几纳米。我们还表明，2D 半导体可以经过独特设计来制造 2D 纳米板场效应晶体管，与具有相似尺寸 2D 和硅的 3D 场效应晶体管相比，其集成密度和驱动电流提高了近 10 倍。