The advancement in semiconductor technology through the integration of more devices on a chip has reached a point where device scaling alone is no longer an efficient way to improve the device performance. One issue lies in the interconnects connecting the transistors, in which the resistivity of metals increases exponentially as their dimensions are scaled down to match those of the transistors. As a result, the total signal processing delay is dominated by the resistance-capacitance (RC) delay from the interconnects rather than the delay from the transistors’ switching speed. This bottleneck has spurred efforts both in academia and industry to explore alternative materials and disruptive device structures. Therefore, we suggest strategies to overcome the RC delay of the interconnects in both material and device aspects.

中文翻译：

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解决互连挑战以增强计算性能


通过在芯片上集成更多器件，半导体技术的进步已经达到了这样一个地步，即仅靠器件扩展不再是提高器件性能的有效方法。一个问题在于连接晶体管的互连，其中金属的电阻率随着其尺寸缩小以匹配晶体管的尺寸而呈指数级增加。因此，总信号处理延迟由互连的电阻电容 （RC） 延迟决定，而不是由晶体管开关速度的延迟决定。这一瓶颈促使学术界和工业界努力探索替代材料和颠覆性的器件结构。因此，我们建议在材料和器件方面克服互连的 RC 延迟的策略。