For TSMC, Geoffrey Yeap and colleagues report a 2 nm logic platform. Based on gate-all-around nanosheet transistors, it features a scalable copper-based redistribution layer and a flat passivation layer, as well as through-silicon vias. Compared with their previous 3 nm technology node, which was reported at the 2022 IEEE International Electron Devices Meeting, this platform offers an increase in chip density of around 1.15 times, and a speed gain of around 15% or a power reduction of around 30%. It is scheduled for mass production in the second half of 2025.

For Intel, Ashish Agrawal and colleagues report gate-all-around ribbon transistors (the Intel version of nanosheet transistors) at a gate length of 6 nm and contacted poly pitch (the spacing between adjacent transistor gates) of 45 nm. They show that electron mobility in the devices does not degrade down to a silicon thickness of 3 nm, below which electron scattering due to surface roughness becomes a problem.

对于 TSMC，Geoffrey Yeap 及其同事报告了一个 2 nm 逻辑平台。它基于全环绕栅极纳米片晶体管，具有可扩展的铜基再分布层和平坦的钝化层，以及硅通孔。与他们之前在 2022 年 IEEE 国际电子器件会议上报告的 3 nm 技术节点相比，该平台的芯片密度提高了约 1.15 倍，速度提高了约 15% 或功耗降低了约 30%。计划于 2025 年下半年量产。

对于英特尔，Ashish Agrawal 及其同事报告了栅极长度为 6 nm 的全环绕栅极带状晶体管（Intel 版本的纳米片晶体管）和 45 nm 的接触多晶间距（相邻晶体管栅极之间的间距）。他们表明，器件中的电子迁移率不会降低到 3 nm 的硅厚度，低于该厚度时，由于表面粗糙度引起的电子散射将成为一个问题。