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Learning to rank quantum circuits for hardware-optimized performance enhancement
Quantum ( IF 5.1 ) Pub Date : 2024-11-27 , DOI: 10.22331/q-2024-11-27-1542
Gavin S. Hartnett, Aaron Barbosa, Pranav S. Mundada, Michael Hush, Michael J. Biercuk, Yuval Baum

We introduce and experimentally test a machine-learning-based method for ranking logically equivalent quantum circuits based on expected performance estimates derived from a training procedure conducted on real hardware. We apply our method to the problem of layout selection, in which abstracted qubits are assigned to physical qubits on a given device. Circuit measurements performed on IBM hardware indicate that the maximum and median fidelities of logically equivalent layouts can differ by an order of magnitude. We introduce a circuit score used for ranking that is parameterized in terms of a physics-based, phenomenological error model whose parameters are fit by training a ranking-loss function over a measured dataset. The dataset consists of quantum circuits exhibiting a diversity of structures and executed on IBM hardware, allowing the model to incorporate the contextual nature of real device noise and errors without the need to perform an exponentially costly tomographic protocol. We perform model training and execution on the 16-qubit $ibmq\_guadalupe$ device and compare our method to two common approaches: random layout selection and a publicly available baseline called Mapomatic. Our model consistently outperforms both approaches, predicting layouts that exhibit lower noise and higher performance. In particular, we find that our best model leads to a $1.8\times$ reduction in selection error when compared to the baseline approach and a $3.2\times$ reduction when compared to random selection. Beyond delivering a new form of predictive quantum characterization, verification, and validation, our results reveal the specific way in which context-dependent and coherent gate errors appear to dominate the divergence from performance estimates extrapolated from simple proxy measures.

中文翻译:


学习对量子电路进行排名,以实现硬件优化的性能增强



我们引入并实验测试了一种基于机器学习的方法,该方法根据在真实硬件上进行的训练程序得出的预期性能估计对逻辑等效的量子电路进行排名。我们将方法应用于布局选择问题,其中抽象的量子比特被分配给给定设备上的物理量子比特。在 IBM 硬件上执行的电路测量表明,逻辑等效布局的最大保真度和中位数可能相差一个数量级。我们引入了一个用于排名的电路分数,该分数根据基于物理的现象学误差模型进行参数化,其参数是通过在测量数据集上训练排名损失函数来拟合的。该数据集由具有多种结构并在 IBM 硬件上执行的量子电路组成,使模型能够整合真实设备噪声和误差的上下文性质,而无需执行成本呈指数级增长的断层扫描协议。我们在 16 量子比特 $ibmq\_guadalupe$ 设备上执行模型训练和执行,并将我们的方法与两种常见方法进行比较:随机布局选择和名为 Mapomatic 的公开可用基线。我们的模型始终优于这两种方法,预测出具有更低噪声和更高性能的布局。特别是,我们发现与基线方法相比,我们的最佳模型导致选择误差减少了 $1.8\times$,与随机选择相比减少了 $3.2\times$。 除了提供一种新形式的预测量子表征、验证和确认之外,我们的结果还揭示了上下文依赖性和相干门误差似乎主导了与从简单代理测量推断的性能估计的分歧的具体方式。
更新日期:2024-11-27
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