The CeO₂-based memristor has attracted significant attention due to its intrinsic resistive switching (RS) properties, large on/off ratio, and great plasticity, making it a promising candidate for artificial synapses. However, significant challenges such as high power consumption and poor device reliability hinder its broad application in neuromorphic microchips. To tackle these issues, in this work, we design a novel bilayer (BL) memristor by integrating a CeO₂-based memristor with a Co-CeO₂ vertically aligned nanocomposite (VAN) layer and compare it with the single layer (SL) memristor. Preliminary electrical testing reveals that the BL memristor offers a reduced set/reset voltage (∼67% lower), a higher on/off ratio (∼5 × 10²), enhanced device reliability, and improved device-to-device variation compared to the SL memristor. Insight from COMSOL simulation, coupled with microstructural analysis, provides a comprehensive elucidation on how the VAN layer facilitates the selective conductive filament (CF) formation. Subsequently, the plasticity of the BL memristor is evaluated through long-term potentiation/depression (LTP/LTD), paired-pulse facilitation (PPF), and spike-time-dependent plasticity (STDP). The spiking neural network (SNN) built upon the BL memristor achieves remarkable accuracy (∼94%) after only 12 iterations, underscoring its potential for high-performance neural networks.

中文翻译：

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基于 CeO2 的忆阻器与垂直排列的纳米复合薄膜的集成：实现高性能电子突触的选择性导电丝形成


基于 CeO₂ 的忆阻器因其固有的电阻开关 （RS） 特性、大开/关比和出色的可塑性而引起了广泛关注，使其成为人工突触的有前途的候选者。然而，高功率消耗和较差的器件可靠性等重大挑战阻碍了其在神经形态微芯片中的广泛应用。为了解决这些问题，在这项工作中，我们通过将基于 CeO₂ 的忆阻器与 Co-CeO₂ 垂直对齐的纳米复合材料 （VAN） 层集成，并将其与单层 （SL） 忆阻器进行比较，设计了一种新型双层 （BL） 忆阻器。初步电气测试表明，与 SL 忆阻器相比，BL 忆阻器具有更低的设置/复位电压（降低 ∼67%）、更高的开/关比（∼5 × 10²）、增强的器件可靠性以及改进的器件间变化。COMSOL 仿真的见解与微观结构分析相结合，全面阐明了 VAN 层如何促进选择性导电丝 （CF） 的形成。随后，通过长时程增强/抑制 （LTP/LTD）、成对脉冲促进 （PPF） 和尖峰时间依赖性塑性 （STDP） 评估 BL 忆阻器的塑性。基于 BL 忆阻器构建的尖峰神经网络 （SNN） 仅在 12 次迭代后就实现了出色的精度 （∼94%），凸显了其高性能神经网络的潜力。