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Integration of high-κ native oxides of gallium for two-dimensional transistors
Nature Electronics ( IF 33.7 ) Pub Date : 2024-11-15 , DOI: 10.1038/s41928-024-01286-x
Kongyang Yi, Wen Qin, Yamin Huang, Yao Wu, Shaopeng Feng, Qiyi Fang, Xun Cao, Ya Deng, Chao Zhu, Xilu Zou, Kah-Wee Ang, Taotao Li, Xinran Wang, Jun Lou, Keji Lai, Zhili Hu, Zhuhua Zhang, Yemin Dong, Kourosh Kalantar-Zadeh, Zheng Liu

The deposition of a metal oxide layer with good dielectric properties is a critical step in fabricating the gate dielectric of transistors based on two-dimensional semiconductors. However, current techniques for depositing ultrathin metal oxide layers on two-dimensional semiconductors suffer from quality issues that can compromise transistor performance. Here, we show that an ultrathin and uniform native oxide of gallium (Ga2O3) that naturally forms on the surface of liquid metals in an ambient environment can be prepared on the surface of molybdenum disulfide (MoS2) by squeeze-printing and surface-tension-driven methods. The Ga2O3 layer possesses a high dielectric constant of around 30 and equivalent oxide thickness of around 0.4 nm. Due to the good dielectric properties and van der Waals integration, MoS2 transistors with Ga2O3 gate dielectrics exhibit a subthreshold swing down to 60 mV dec−1, an on/off ratio of 108 and a gate leakage down to around 4 × 10−7 A cm−2.



中文翻译:


集成高 κ 天然镓氧化物用于二维晶体管



沉积具有良好介电性能的金属氧化物层是制造基于二维半导体的晶体管栅极电介质的关键步骤。然而,目前在二维半导体上沉积超薄金属氧化物层的技术存在质量问题,可能会影响晶体管性能。在这里,我们表明,在周围环境中液态金属表面自然形成的超薄且均匀的天然氧化镓 (Ga2O3) 可以通过挤压印刷和表面张力驱动方法在二硫化钼 (MoS2) 的表面上制备。Ga2O3 层具有约 30 的高介电常数和约 0.4 nm 的等效氧化物厚度。由于良好的介电性能和范德华集成,具有 Ga2O3 栅极电介质的 MoS2 晶体管表现出低至 60 mV dec-1 的亚阈值摆幅、108 的开/关比和 4 × 10-7 A cm-2 左右的栅极泄漏。

更新日期:2024-11-15
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