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High-performance p-type field-effect transistors using substitutional doping and thickness control of two-dimensional materials
Nature Electronics ( IF 33.7 ) Pub Date : 2024-11-06 , DOI: 10.1038/s41928-024-01265-2
Mayukh Das, Dipanjan Sen, Najam U Sakib, Harikrishnan Ravichandran, Yongwen Sun, Zhiyu Zhang, Subir Ghosh, Pranavram Venkatram, Shiva Subbulakshmi Radhakrishnan, Alexander Sredenschek, Zhuohang Yu, Kalyan Jyoti Sarkar, Muhtasim Ul Karim Sadaf, Kalaiarasan Meganathan, Andrew Pannone, Ying Han, David Emanuel Sanchez, Divya Somvanshi, Zdenek Sofer, Mauricio Terrones, Yang Yang, Saptarshi Das

In silicon field-effect transistors (FETs), degenerate doping of the channel beneath the source and drain regions is used to create high-performance n- and p-type devices by reducing the contact resistance. Two-dimensional semiconductors have, in contrast, relied on metal-work-function engineering. This approach has led to the development of effective n-type 2D FETs due to the Fermi-level pinning occurring near the conduction band, but it is challenging with p-type FETs. Here we show that the degenerate p-type doping of molybdenum diselenide and tungsten diselenide—achieved through substitutional doping with vanadium, niobium and tantalum—can reduce the contact resistance to as low as 95 Ω µm in multilayers. This, though, comes at the cost of poor electrostatic control, and we find that the doping effectiveness—and its impact on electrostatic control—is reduced in thinner layers due to strong quantum confinement effects. We, therefore, develop a high-performance p-type 2D molybdenum diselenide FET using a layer-by-layer thinning method to create a device with thin layers at the channel and thick doped layers at the contact regions.



中文翻译:


使用二维材料的替代掺杂和厚度控制的高性能 p 型场效应晶体管



在硅场效应晶体管 (FET) 中,源极和漏极区域下方的沟道简并掺杂用于通过降低接触电阻来制造高性能的 n 型和 p 型器件。相比之下,二维半导体依赖于金属加工功能工程。由于费米能级固定发生在导带附近,这种方法导致了有效的 n 型 2D FET 的发展,但对于 p 型 FET 来说却具有挑战性。在这里,我们表明,通过钒、铌和钽的替代掺杂实现二硒化钼和二硒化钨的简并 p 型掺杂可以将多层中的接触电阻降低到低至 95 Ω μm。然而,这是以静电控制不佳为代价的,我们发现,由于强大的量子限制效应,掺杂有效性及其对静电控制的影响在较薄的层中会降低。因此,我们使用逐层减薄方法开发了一种高性能 p 型 2D 二硒化钼 FET,以制造一种在通道处具有薄层,在接触区域具有厚掺杂层的器件。

更新日期:2024-11-06
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