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A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a $-$62.1-dBc Fractional Spur
IEEE Journal of Solid-State Circuits ( IF 4.6 ) Pub Date : 2024-10-23 , DOI: 10.1109/jssc.2024.3477498 Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada
中文翻译：
基于级联小数分频器和伪差分 DTC 的 DPD/无抖动 DPLL，可实现 $-62.1-dBc 小数杂散
更新日期：2024-10-23
IEEE Journal of Solid-State Circuits ( IF 4.6 ) Pub Date : 2024-10-23 , DOI: 10.1109/jssc.2024.3477498 Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada
中文翻译：
基于级联小数分频器和伪差分 DTC 的 DPD/无抖动 DPLL，可实现 $-62.1-dBc 小数杂散
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