Strain engineering has played a key role in modern silicon electronics, having been introduced as a mobility booster in the 1990s and commercialized in the early 2000s. Achieving similar advances with two-dimensional (2D) semiconductors in a complementary metal–oxide–semiconductor (CMOS)-compatible manner could improve the industrial viability of 2D material transistors. Here, we show that silicon nitride capping layers can impart strain to monolayer molybdenum disulfide (MoS₂) transistors on conventional silicon substrates, improving their performance with a CMOS-compatible approach, at a low thermal budget of 350 °C. Strained back-gated and dual-gated MoS₂ transistors exhibit median increases in on-state current of up to 60% and 45%, respectively. The greatest improvements are found when reducing both transistor channels and contacts from micrometre-scale to 200 nm, reaching saturation currents of 488 µA µm⁻¹ in devices with just 400 nm contact pitch. Simulations show that the performance enhancement is mainly due to tensile strain lowering the contact Schottky barriers, and that further reducing device dimensions, including contacts, could lead to additional increases in strain and performance.

应变工程在现代硅电子学中发挥了关键作用，在 1990 年代作为移动助推器推出，并在 2000 年代初商业化。以互补金属氧化物半导体 （CMOS） 兼容的方式使用二维 （2D） 半导体实现类似的进步可以提高 2D 材料晶体管的工业可行性。在这里，我们展示了氮化硅覆盖层可以向传统硅衬底上的单层二硫化钼 （MoS₂） 晶体管施加应变，从而在 350 °C 的低热预算下通过兼容 CMOS 的方法提高其性能。 应变背门和双门 MoS₂ 晶体管的导通电流中位数分别增加高达 60% 和 45%。当晶体管通道和触点从微米级减少到 200 nm 时，发现最大的改进是在只有 400 nm 触点间距的器件中达到 488 μA ^μm-1 的饱和电流。仿真表明，性能增强主要是由于拉伸应变降低了接触肖特基势垒，进一步减小器件尺寸（包括触点）可能会导致应变和性能的额外增加。