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A 28-nm 16-kb Aggregation and Combination Computing-in-Memory Macro With Dual-Level Sparsity Modulation and Sparse-Tracking ADCs for GCNs
IEEE Journal of Solid-State Circuits ( IF 4.6 ) Pub Date : 2024-10-16 , DOI: 10.1109/jssc.2024.3472115 Zhaoyang Zhang, Yanqi Zhang, Feiran Liu, Zhichao Liu, Yinhai Gao, Yuchen Ma, Yutong Zhang, An Guo, Tianzhu Xiong, Jinwu Chen, Xi Chen, Bo Wang, Yuchen Tang, Jun Yang, Xin Si
中文翻译：
一个 28 纳米 16 KB 聚合和组合内存计算宏，具有用于 GCN 的双级稀疏调制和稀疏跟踪 ADC
更新日期：2024-10-16
IEEE Journal of Solid-State Circuits ( IF 4.6 ) Pub Date : 2024-10-16 , DOI: 10.1109/jssc.2024.3472115 Zhaoyang Zhang, Yanqi Zhang, Feiran Liu, Zhichao Liu, Yinhai Gao, Yuchen Ma, Yutong Zhang, An Guo, Tianzhu Xiong, Jinwu Chen, Xi Chen, Bo Wang, Yuchen Tang, Jun Yang, Xin Si
中文翻译：
一个 28 纳米 16 KB 聚合和组合内存计算宏，具有用于 GCN 的双级稀疏调制和稀疏跟踪 ADC
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