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Inverse-designed taper configuration for the enhancement of integrated 1 × 4 silicon photonic power splitters
Nanophotonics ( IF 6.5 ) Pub Date : 2024-09-09 , DOI: 10.1515/nanoph-2024-0295 Seokjin Hong 1 , Jinhyeong Yoon 1 , Junhyeong Kim 1 , Berkay Neseli 1 , Jae-Yong Kim 1 , Hyo-Hoon Park 1 , Hamza Kurt 1
Nanophotonics ( IF 6.5 ) Pub Date : 2024-09-09 , DOI: 10.1515/nanoph-2024-0295 Seokjin Hong 1 , Jinhyeong Yoon 1 , Junhyeong Kim 1 , Berkay Neseli 1 , Jae-Yong Kim 1 , Hyo-Hoon Park 1 , Hamza Kurt 1
Affiliation
Once light is coupled to a photonic chip, its efficient distribution in terms of power splitting throughout silicon photonic circuits is very crucial. We present two types of 1 × 4 power splitters with different splitting ratios of 1:1:1:1 and 2:1:1:2. Various taper configurations were compared and analyzed to find the suitable configuration for the power splitter, and among them, parabolic tapers were chosen. The design parameters of the power splitter were determined by means of solving inverse design problems via incorporating particle swarm optimization that allows for overcoming the limitation of the intuition-based brute-force approach. The front and rear portions of the power splitters were optimized sequentially to alleviate local minima issues. The proposed power splitters have a compact footprint of 12.32 × 5 μm2 and can be fabricated through a CMOS-compatible fabrication process. Two-stage power splitter trees were measured to enhance reliability in an experiment. As a result, the power splitter with a splitting ratio of 1:1:1:1 exhibited an experimentally measured insertion loss below 0.61 dB and an imbalance below 1.01 dB within the bandwidth of 1,518–1,565 nm. Also, the power splitter with a splitting ratio of 2:1:1:2 showed an insertion loss below 0.52 dB and a targeted imbalance below 1.15 dB within the bandwidth of 1,526–1,570 nm. Such inverse-designed power splitters can be an essential part of many large-scale photonic circuits including optical phased arrays, programmable photonics, and photonic computing chips.
中文翻译:
用于增强集成 1 × 4 硅光子功率分配器的逆向设计锥形配置
一旦光耦合到光子芯片,其在整个硅光子电路中功率分配的有效分配就非常关键。我们提供两种类型的 1 × 4 功率分配器,具有不同的分配比:1:1:1:1 和 2:1:1:2。对各种锥度配置进行了比较和分析,找到了适合功率分配器的配置,其中选择了抛物线锥度。功率分配器的设计参数是通过结合粒子群优化解决逆设计问题来确定的,该优化可以克服基于直觉的蛮力方法的局限性。功率分配器的前部和后部按顺序进行优化,以缓解局部最小值问题。所提出的功率分配器具有 12.32 × 5 μm2 的紧凑尺寸,并且可以通过 CMOS 兼容的制造工艺来制造。在实验中测量了两级功率分配器树以提高可靠性。结果,分光比为1:1:1:1的功率分配器在1,518-1,565 nm带宽内的实验测量插入损耗低于0.61 dB,不平衡度低于1.01 dB。此外,分光比为 2:1:1:2 的功率分配器在 1,526–1,570 nm 带宽内的插入损耗低于 0.52 dB,目标不平衡度低于 1.15 dB。这种逆向设计的功率分配器可以成为许多大规模光子电路的重要组成部分,包括光学相控阵、可编程光子学和光子计算芯片。
更新日期:2024-09-09
中文翻译:
用于增强集成 1 × 4 硅光子功率分配器的逆向设计锥形配置
一旦光耦合到光子芯片,其在整个硅光子电路中功率分配的有效分配就非常关键。我们提供两种类型的 1 × 4 功率分配器,具有不同的分配比:1:1:1:1 和 2:1:1:2。对各种锥度配置进行了比较和分析,找到了适合功率分配器的配置,其中选择了抛物线锥度。功率分配器的设计参数是通过结合粒子群优化解决逆设计问题来确定的,该优化可以克服基于直觉的蛮力方法的局限性。功率分配器的前部和后部按顺序进行优化,以缓解局部最小值问题。所提出的功率分配器具有 12.32 × 5 μm2 的紧凑尺寸,并且可以通过 CMOS 兼容的制造工艺来制造。在实验中测量了两级功率分配器树以提高可靠性。结果,分光比为1:1:1:1的功率分配器在1,518-1,565 nm带宽内的实验测量插入损耗低于0.61 dB,不平衡度低于1.01 dB。此外,分光比为 2:1:1:2 的功率分配器在 1,526–1,570 nm 带宽内的插入损耗低于 0.52 dB,目标不平衡度低于 1.15 dB。这种逆向设计的功率分配器可以成为许多大规模光子电路的重要组成部分,包括光学相控阵、可编程光子学和光子计算芯片。