Multichips paralleled insulated gate bipolar transistor (IGBT) power modules are widely employed in industrial and automotive power conversion systems. The asymmetry of the circuit topology and the differences in chip characteristics are the main reasons for the unbalanced current distribution among parallel chips, leading to excessive electrical stress in power modules, which in turn forces the power modules to operate at a reduced rated current. Additionally, the unbalanced current distribution inevitably results in different chip losses, which are further amplified under high current loading conditions, causing some chips to be overheated, and significantly reducing the reliability. Optimizing the circuit topology is a common method to improve current distribution, but global changes often entail higher costs and longer development cycles. Moreover, the electrical parasitic of the fast recovery diodes (FRD) chip branches are not given sufficient attention in circuit topology research. Under rectification and blocked conditions in electric vehicles, FRDs often become the bottleneck for lifespan due to excessively high junction temperatures. Therefore, this article conducts a comparative analysis of the circuit parasitic in IGBT and FRD loops with several typical layouts, without changing the substrate and chip dimensions, and proposes a current sharing slot structure design to balance the parasitic parameters. Compared with the direct bonded copper (DBC) layout of the typical EconoDUAL power module, the optimized module reduces the current imbalance of FRD from 45.5% to 11.6% and the switching loss can be reduced by 8.6%. By adopting the current sharing groove, the parasitic parameter distribution can be further improved while maintaining a fixed DBC layout, considering the IGBT and FRD branches in concert. Finally, the steady-state and transient current sharing characteristics were verified under constant current and inverter conditions. Under constant current conditions, the temperature difference of FRD in the upper and lower parallel layout modules was reduced by 16.7 °C, and the junction temperature of IGBT was significantly lowered. Under inverter conditions, the highest junction temperature of the columnar layout modules could be reduced by 10 °C, and the temperature difference of FRD decreased by 62%. This article significantly optimizes the current imbalance issue through layout design, reduces the thermal equilibrium difference of the module under application conditions, and is conducive to improving the output capacity and fatigue life of the module, providing a solution for the design of power modules with high junction temperature operation capability and high-reliability.

中文翻译：

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多芯片并联 IGBT 模块均流优化与验证


多芯片并联绝缘栅双极晶体管（IGBT）功率模块广泛应用于工业和汽车功率转换系统。电路拓扑的不对称和芯片特性的差异是造成并联芯片之间电流分布不平衡的主要原因，导致功率模块中产生过大的电应力，进而迫使功率模块工作在降低的额定电流下。此外，电流分布不平衡不可避免地会导致不同的芯片损耗，在大电流负载条件下，损耗进一步放大，导致部分芯片过热，可靠性显着降低。优化电路拓扑是改善电流分布的常用方法，但全局变化往往会带来更高的成本和更长的开发周期。此外，快速恢复二极管（FRD）芯片支路的电寄生在电路拓扑研究中没有得到足够的重视。在电动汽车的整流和堵转条件下，FRD常常因结温过高而成为寿命瓶颈。因此，本文在不改变基板和芯片尺寸的情况下，对几种典型布局的IGBT和FRD环路中的电路寄生进行了比较分析，并提出了均流槽结构设计来平衡寄生参数。与典型EconoDUAL功率模块的直接敷铜（DBC）布局相比，优化后的模块将FRD的电流不平衡度从45.5%降低至11.6%，开关损耗可降低8.6%。 通过采用均流槽，在保持固定DBC布局的同时，可以进一步改善寄生参数分布，同时考虑IGBT和FRD支路。最后，在恒流和逆变条件下验证了稳态和瞬态均流特性。恒流条件下，上下并联模块FRD温差降低了16.7℃，IGBT结温明显降低。在逆变器条件下，柱状布局组件的最高结温可降低10℃，FRD温差降低62%。本文通过版图设计显着优化了电流不平衡问题，降低了模块在应用条件下的热平衡差异，有利于提高模块的输出能力和疲劳寿命，为高功率电源模块的设计提供了解决方案。结温运行能力和高可靠性。