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A 6.5-to-8-GHz Cascaded Dual-Fractional-$N$ Digital PLL Achieving $-$52.79-dBc Fractional Spur With 50-MHz Reference
IEEE Journal of Solid-State Circuits ( IF 4.6 ) Pub Date : 2024-08-30 , DOI: 10.1109/jssc.2024.3447021 Dingxin Xu 1 , Yuncheng Zhang 1 , Hongye Huang 1 , Zheng Sun 1 , Bangan Liu 1 , Ashbir Aviat Fadila 1 , Junjun Qiu 1 , Zezheng Liu 1 , Wenqian Wang 1 , Yuang Xiong 1 , Waleed Madany 1 , Atsushi Shirane 1 , Kenichi Okada 1
中文翻译：
6.5 至 8 GHz 级联双小数 N$ 数字 PLL 在 50 MHz 参考下实现 52.79 dBc 小数杂散
更新日期：2024-08-30
IEEE Journal of Solid-State Circuits ( IF 4.6 ) Pub Date : 2024-08-30 , DOI: 10.1109/jssc.2024.3447021 Dingxin Xu 1 , Yuncheng Zhang 1 , Hongye Huang 1 , Zheng Sun 1 , Bangan Liu 1 , Ashbir Aviat Fadila 1 , Junjun Qiu 1 , Zezheng Liu 1 , Wenqian Wang 1 , Yuang Xiong 1 , Waleed Madany 1 , Atsushi Shirane 1 , Kenichi Okada 1
Affiliation
中文翻译：
6.5 至 8 GHz 级联双小数 N$ 数字 PLL 在 50 MHz 参考下实现 52.79 dBc 小数杂散
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