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A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk
IEEE Journal of Solid-State Circuits ( IF 4.6 ) Pub Date : 2024-08-12 , DOI: 10.1109/jssc.2024.3437168 Luca Ricci 1 , Gabriele Bè 1 , Michele Rocco 1 , Lorenzo Scaletti 2 , Gabriele Zanoletti 1 , Luca Bertulessi 1 , Andrea L. Lacaita 1 , Salvatore Levantino 1 , Carlo Samori 1 , Andrea Bonfanti 1
中文翻译：
具有嵌入式后台校准功能的 2GS/s 时间交错 ADC 和可减少通道间串扰的新颖参考缓冲器
更新日期：2024-08-12
IEEE Journal of Solid-State Circuits ( IF 4.6 ) Pub Date : 2024-08-12 , DOI: 10.1109/jssc.2024.3437168 Luca Ricci 1 , Gabriele Bè 1 , Michele Rocco 1 , Lorenzo Scaletti 2 , Gabriele Zanoletti 1 , Luca Bertulessi 1 , Andrea L. Lacaita 1 , Salvatore Levantino 1 , Carlo Samori 1 , Andrea Bonfanti 1
Affiliation
中文翻译：
具有嵌入式后台校准功能的 2GS/s 时间交错 ADC 和可减少通道间串扰的新颖参考缓冲器
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