The semiconductor industry is transitioning to the ‘More Moore’ era, driven by the adoption of three-dimensional (3D) integration schemes surpassing the limitations of traditional two-dimensional scaling. Although innovative packaging solutions have made 3D integrated circuits (ICs) commercially viable, the inclusion of through-silicon vias and microbumps brings about increased area overhead and introduces parasitic capacitances that limit overall performance. Monolithic 3D integration (M3D) is regarded as the future of 3D ICs, yet its application faces hurdles in silicon ICs due to restricted thermal processing budgets in upper tiers, which can degrade device performance. To overcome these limitations, emerging materials like carbon nanotubes and two-dimensional semiconductors have been integrated into the back end of silicon ICs. Here we report the M3D integration of complementary WSe₂ FETs, in which n-type FETs are placed in tier 1 and p-type FETs are placed in tier 2. In particular, we achieve dense and scaled integration through 300 nm vias with a pitch of <1 µm, connecting more than 300 devices in tiers 1 and 2. Moreover, we have effectively implemented vertically integrated logic gates, encompassing inverters, NAND gates and NOR gates. Our demonstration highlights the two-dimensional materials’ role in advancing M3D integration in complementary metal–oxide–semiconductor circuits.

在三维 (3D) 集成方案的采用超越了传统二维缩放的限制的推动下，半导体行业正在过渡到“更多摩尔”时代。尽管创新的封装解决方案使 3D 集成电路 (IC) 具有商业可行性，但硅通孔和微凸块的加入会增加面积开销，并引入限制整体性能的寄生电容。单片 3D 集成 (M3D) 被认为是 3D IC 的未来，但由于上层的热处理预算有限，其应用在硅 IC 方面面临障碍，这可能会降低器件性能。为了克服这些限制，碳纳米管和二维半导体等新兴材料已被集成到硅 IC 的后端。在这里，我们报告了互补 WSe ₂ FET 的 M3D 集成，其中 n 型 FET 放置在第 1 层，p 型 FET 放置在第 2 层。特别是，我们通过间距为 300 nm 的通孔实现了密集和规模化的集成<1 µm，连接第 1 层和第 2 层的 300 多个器件。此外，我们有效地实现了垂直集成逻辑门，包括反相器、与非门和或非门。我们的演示强调了二维材料在推进互补金属氧化物半导体电路中 M3D 集成方面的作用。