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A Dual Channel Push Pull Clamped-Interlock Resonant Gate Driver for the Secondary-Side MOSFETs of LLC-DCX
IEEE Transactions on Industrial Electronics ( IF 7.5 ) Pub Date : 7-23-2024 , DOI: 10.1109/tie.2024.3419221
Ziyan Zhou 1 , Qiang Luo 1 , Yufan Wang 1 , Yuefei Sun 1 , Qinsong Qian 1 , Weifeng Sun 1
Affiliation  

The LLC dc transformer (LLC-DCX), due to its soft-switching characteristics, achieves high-efficiency energy transfer at high frequencies and is extensively used in high power density applications. However, the drive loss of conventional drive integrated circuits (ICs) is proportional to the switching frequency, leading to disproportionately high gate drive loss at higher frequencies, thereby limiting further increases in the LLC-DCX switching frequency. In this article, a dual channel push pull clamped-interlock resonant gate driver (DPCRGD) is introduced for driving the secondary-side metal-oxide -semiconductor field effect transistor (MOSFETs) of LLC-DCX. The proposed DPCRGD provides two complementary driving signals for LLC-DCX. Compared to conventional voltage source drivers and existing research, the RGD presented here demonstrates lower drive loss and a smaller footprint. This article details the operational principles, loss analysis, parameter optimization design, and comparative studies of the DPCRGD. Ultimately, a prototype operating at 1.3 MHz with an output power of 48 V_6V/30 A was developed. Experimental results validate the effectiveness of the proposed DPCRGD, showing a reduction of gate drive power loss by nearly 88% and a 49% decrease in footprint compared to conventional voltage source driving circuits.

中文翻译:


用于 LLC-DCX 次级侧 MOSFET 的双通道推挽钳位互锁谐振栅极驱动器



LLC直流变压器(LLC-DCX)由于其软开关特性,可实现高频下的高效能量传输,广泛应用于高功率密度应用。然而,传统驱动集成电路 (IC) 的驱动损耗与开关频率成正比,导致较高频率下的栅极驱动损耗不成比例地高,从而限制了 LLC-DCX 开关频率的进一步提高。在本文中,介绍了一种双通道推挽钳位互锁谐振栅极驱动器 (DPCRGD),用于驱动 LLC-DCX 的次级侧金属氧化物半导体场效应晶体管 (MOSFET)。所提出的 DPCRGD 为 LLC-DCX 提供两个互补的驱动信号。与传统的电压源驱动器和现有研究相比,此处介绍的 RGD 表现出较低的驱动损耗和较小的占地面积。本文详细介绍了DPCRGD的工作原理、损耗分析、参数优化设计和比较研究。最终,开发了工作频率为 1.3 MHz、输出功率为 48 V_6V/30 A 的原型机。实验结果验证了所提出的 DPCRGD 的有效性,与传统电压源驱动电路相比,栅极驱动功率损耗减少了近 88%,占地面积减少了 49%。
更新日期:2024-08-22
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