Three-dimensional (3D) stacking of chiplets into a single system-in-package can lead to scaling opportunities beyond the conventional scaling of device dimensions. In this approach, computing elements are connected in a face-to-face die configuration by a silicon interposer using through-silicon via (TSV) technology and microbumps. However, process optimization is crucial to achieve good responsiveness and suppression of transient current during high-performance workloads, as well as to improve noise reduction. Christopher Pelto and colleagues now report a passive silicon interposer containing a high-density metal–insulator–metal decoupling capacitor.

The researchers — who are based at Intel Corporation — demonstrate a silicon interposer connected to top chiplets using silicon interposer bumps with a diameter of 18 μm and minimum pitch of 36 μm. Integrating a capacitor based on a high-κ oxide and titanium nitride (TiN) electrodes allows on-die voltage regulation, reduces the voltage drop, suppresses noise and improves power delivery to all system components. Using Intel’s 2.5D Foveros technology for 3D stacking, Pelto and colleagues were able to integrate a central processing unit, graphics processing unit and system-on-chip on multiple process nodes with high reliability and power integrity.

将小芯片三维 (3D) 堆叠到单个系统级封装中可以带来超出传统器件尺寸缩放的缩放机会。在这种方法中，计算元件通过使用硅通孔 (TSV) 技术和微凸块的硅中介层以面对面的芯片配置方式连接。然而，工艺优化对于在高性能工作负载期间实现良好的响应能力和瞬态电流抑制以及改善降噪至关重要。 Christopher Pelto 及其同事现在报告了一种包含高密度金属-绝缘体-金属去耦电容器的无源硅中介层。

英特尔公司的研究人员展示了一种硅中介层，该硅中介层使用直径为 18 μm、最小间距为 36 μm 的硅中介层凸块连接到顶部小芯片。集成基于高κ氧化物和氮化钛 (TiN) 电极的电容器可实现片上电压调节、降低电压降、抑制噪声并改善所有系统组件的功率传输。利用英特尔的 2.5D Foveros 3D 堆叠技术，Pelto 及其同事能够在多个工艺节点上集成中央处理单元、图形处理单元和片上系统，并具有高可靠性和电源完整性。