Rising demands on wireless communications technology means that the development of next-generation wireless systems is increasingly focused on the use of millimetre and sub-terahertz frequency bands. Chenxin Liu and colleagues at the Tokyo Institute of Technology now report a transceiver chipset that is made using a 65 nm complementary metal–oxide–semiconductor (CMOS) process and operates in the D-band (114–170 GHz) with a 56 GHz bandwidth.

The chipset contains several components, including an 8-way low-Q power amplifier, a 2-way low-Q low-noise amplifier, mixers and cascaded distributed amplifiers to improve the bandwidth and linearity. When operating in a single-input single-output mode, it can achieve an over-the-air data rate of 200 Gb s^–1 with a bit-error rate under 10^–3. In a 4 × 4 multiple-input multiple-output (MIMO) mode using orthogonal frequency-division multiplexing, it can achieve a data rate of 640 Gb s^–1.

对无线通信技术的需求不断增长，这意味着下一代无线系统的开发越来越集中在毫米和次太赫兹频段的使用上。东京工业大学的 Chenxin Liu 和同事现在报道了一种收发器芯片组，该芯片组采用 65 nm 互补金属氧化物半导体 （CMOS） 工艺制成，在 D 波段 （114–170 GHz） 运行，带宽为 56 GHz。

该芯片组包含多个组件，包括一个 8 路低 Q 功率放大器、一个 2 路低 Q 低噪声放大器、混频器和级联分布式放大器，以提高带宽和线性度。当在单输入单输出模式下运行时，它可以实现 200 Gb s^–1 的空口数据速率，误码率低于 10^–3。在使用正交频分复用的 4 × 4 多输入多输出 （MIMO） 模式下，它可以实现 640 Gb s^–1 的数据速率。