Enhancing the performance of noisy quantum processors requires improving our understanding of error mechanisms and the ways to overcome them. A judicious selection of qubit design parameters plays a pivotal role in improving the performance of quantum processors. In this study, we identify optimal ranges for qubit design parameters, grounded in comprehensive noise modeling. To this end, we also analyze the effect of a charge-parity switch caused by quasiparticles on a two-qubit gate. Due to the utilization of the second excited state of a transmon, where the charge dispersion is significantly larger, a charge-parity switch will affect the conditional phase of the two-qubit gate. We derive an analytical expression for the infidelity of a diabatic controlled-Z gate and see effects of similar magnitude in adiabatic controlled-phase gates in the tunable coupler architecture. Moreover, we show that the effect of a charge-parity switch can be the dominant quasiparticle-related error source of a two-qubit gate. We also demonstrate that charge-parity switches induce a residual longitudinal interaction between qubits in a tunable-coupler circuit. Furthermore, we introduce a performance metric for quantum circuit execution, encompassing the fidelity and number of single- and two-qubit gates in an algorithm, as well as the state preparation fidelity. This comprehensive metric, coupled with a detailed noise model, enables us to determine an optimal range for the qubit design parameters, as confirmed by numerical simulation. Our systematic analysis offers insights and serves as a guiding framework for the development of the next generation of transmon-based quantum processors.

提高噪声量子处理器的性能需要提高我们对错误机制及其克服方法的理解。明智地选择量子位设计参数对于提高量子处理器的性能起着关键作用。在这项研究中，我们以综合噪声模型为基础，确定了量子位设计参数的最佳范围。为此，我们还分析了准粒子引起的电荷奇偶校验开关对双量子位门的影响。由于利用了传输通道的第二激发态，其中电荷色散明显更大，因此电荷奇偶校验开关将影响双量子位门的条件相位。我们推导了非绝热控制 Z 门的不保真度的分析表达式，并在可调谐耦合器架构中的绝热控制相位门中看到了类似幅度的影响。此外，我们表明电荷奇偶校验开关的影响可能是双量子位门的主要准粒子相关误差源。我们还证明了电荷奇偶校验开关会引起可调谐耦合器电路中量子位之间的残余纵向相互作用。此外，我们引入了量子电路执行的性能指标，包括算法中单量子位门和双量子位门的保真度和数量，以及状态准备保真度。这种综合指标与详细的噪声模型相结合，使我们能够确定量子位设计参数的最佳范围，正如数值模拟所证实的那样。我们的系统分析提供了见解，并为下一代基于 Transmon 的量子处理器的开发提供了指导框架。