Integrating thin atomic-layer-deposited dielectrics with two-dimensional (2D) semiconductors could be used to fabricate 2D transistors with sub-1 nm capacitance-equivalent thicknesses. However, non-uniform nucleation from atomic-layer deposition on inert surfaces and subsequent high-energy metal evaporation can make atomically thin dielectrics non-insulating. Here, we report a bismuth-oxide-assisted chemical vapour deposition method to synthesize single-crystalline metal nanosheets with atomically flat surfaces. The nanosheets grow vertically on a substrate and can be easily transferred to a target substrate through polymer-free mechanical pressing. We show that palladium nanosheets offer an excellent surface for atomic-layer deposition of flat aluminium oxide (Al₂O₃) and hafnium oxide (HfO₂) dielectrics with sub-3 nm thicknesses. These can then be laminated onto few-layer molybdenum disulfide (MoS₂) as a gate stack with a capacitance-equivalent thickness of 0.9 nm and a capacitance density of around 3.9 μF cm⁻². Our MoS₂ top-gated transistors with a 2-nm-thick Al₂O₃ or HfO₂ dielectric exhibit leakage currents of 10⁻⁶ A cm⁻², low operating voltages of around 0.45 V and a hysteresis of less than 1 mV.

将薄原子层沉积电介质与二维 (2D) 半导体集成可用于制造电容等效厚度低于 1 nm 的 2D 晶体管。然而，惰性表面上原子层沉积和随后的高能金属蒸发产生的不均匀成核可能会使原子薄电介质变得不绝缘。在这里，我们报告了一种氧化铋辅助化学气相沉积方法来合成具有原子级平坦表面的单晶金属纳米片。纳米片在基板上垂直生长，并且可以通过无聚合物机械压制轻松转移到目标基板上。我们表明，钯纳米片为厚度低于 3 nm 的平面氧化铝 (Al ₂ O ₃ ) 和氧化铪 (HfO ₂ ) 电介质的原子层沉积提供了优异的表面。然后可以将它们层压到几层二硫化钼（MoS ₂ ）上作为栅极堆叠，其电容等效厚度为0.9 nm，电容密度约为3.9 μF cm ^-2 。我们的 MoS ₂顶栅晶体管具有 2 nm 厚的 Al ₂ O ₃或 HfO ₂电介质，具有 10 ^-6 A cm ^-2的漏电流、约 0.45 V 的低工作电压和小于 1 mV 的磁滞。