Yuan Liu and colleagues at Hunan University now report a one-step van der Waals integration method for the monolithic 3D integration of 2D materials. In their approach, all the components of the circuit tier are fabricated on a sacrificial wafer. This includes chemical vapour deposition-grown MoS₂, the drain and gate electrodes, the gate dielectric (10-nm-thick Al₂O₃) and inter-tier dielectric, and vias. The prefabricated circuit is then removed from the sacrificial wafer and mechanically laminated onto the target 2D surface at a temperature of 120 °C.

The researchers demonstrate the transfer of 2-inch circuit tiers, and stacks of up to 10 tiers thick do not show any apparent degradation of the performance of the MoS₂ transistors in the bottom layers. The alignment of the circuit tiers is achieved by using a transparent polydimethylsiloxane stamp and an optical microscope, with an alignment resolution of about 0.5 μm. However, Liu and colleagues argue that similar alignment processes used in photolithography could be adapted to improve this alignment resolution.

湖南大学的 Yuan Liu 及其同事现在报告了一种用于 2D 材料整体 3D 集成的一步范德华积分方法。在他们的方法中，电路层的所有组件都在牺牲晶圆上制造。这包括化学气相沉积生长的 MoS ₂ 、漏极和栅极、栅极电介质（10 nm 厚的 Al ₂ O ₃ ）和中间层。 -层电介质和过孔。然后将预制电路从牺牲晶圆上移除，并在 120 °C 的温度下机械层压到目标 2D 表面上。

研究人员演示了 2 英寸电路层的转移，以及高达 10 层厚度的堆叠并没有表现出底层 MoS ₂ 晶体管性能的任何明显下降。电路层的对准是通过使用透明的聚二甲基硅氧烷印模和光学显微镜来实现的，对准分辨率约为0.5μm。然而，刘和同事认为，可以采用光刻中使用的类似对准工艺来提高这种对准分辨率。