This article presents a highly integrated hybrid dc–dc converter with a 24-V input, employing the interleaved-inductor multiple step-down (IL-MSD) topology. The proposed design ensures symmetric power-stage operations, addressing inductor current ( $I_{L}$ ) imbalance without complex regulation control. It also optimizes current distribution among internal conduction branches, reducing conduction losses and input capacitor requirements. In addition, we propose an on-chip gate-driving scheme utilizing a high-voltage (HV) floating current (HVFC) source and HV charge storage technique, eliminating external bootstrap capacitors and extra HV supplies. Fabricated in a 180-nm BCD process, the converter chip integrates all-N-type power switches, gate drivers (GDs), startup/pre-charge circuits, and control blocks within a 4.7-mm2 footprint. Using two 1- $\mu \text{H}$ compact inductors and four 1- $\mu \text{F}$ flying capacitors, the converter regulated a 1–3.5-V output from a 24-V input with a peak efficiency of 90.4% under a 1.2-A load. The maximum load current reaches 5 A with an 82% efficiency. The achieved on-chip and overall power densities are 3.51 and 0.62 W/mm3, respectively.

中文翻译：

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具有固有电流均衡特性的 24V 输入高度集成交错电感器多路降压混合 DC-DC 转换器


本文介绍了一种具有 24V 输入的高度集成混合 DC-DC 转换器，采用交错电感器多重降压 (IL-MSD) 拓扑。所提出的设计确保对称功率级操作，解决电感器电流（ $I_{L}$ ）不平衡，无需复杂的调节控制。它还优化了内部传导分支之间的电流分布，减少传导损耗和输入电容器要求。此外，我们提出了一种利用高压（HV）浮动电流（HVFC）源和HV电荷存储技术的片上栅极驱动方案，消除了外部自举电容器和额外的HV电源。该转换器芯片采用 180 nm BCD 工艺制造，在 4.7 mm2 占位面积内集成了全 N 型电源开关、栅极驱动器 (GD)、启动/预充电电路和控制块。使用两个 1- $\mu \文本{H}$紧凑型电感器和四个 1- $\mu \文本{F}$该转换器通过 24V 输入调节 1–3.5V 输出，在 1.2A 负载下峰值效率为 90.4%。最大负载电流达到 5 A，效率为 82%。实现的片上功率密度和总体功率密度分别为 3.51 和 0.62 W/mm3。